Allwinner F1C200s用户手册v1.2：完整版技术指南

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"《Allwinner F1C200s 用户手册 v1.2》是Allwinner Technology Co., Ltd.于2019年7月22日发布的官方文档，适用于其F1C200S芯片系列。该手册是版权受保护的作品，未经Allwinner书面许可，不得擅自复制或部分复制。文档的声明强调了以下几点： 1. 版权归属：文档是Allwinner Technology Co., Ltd.的原创作品，享有全部知识产权。 2. 文档完整性：这是一份完整版的手册，提供了关于F1C200s芯片的详细规格、电路设计和使用指南，旨在确保用户正确和安全地操作这款芯片。 3. 责任与免责声明：Allwinner Technology不对手册中的信息准确性负责，也不承担因使用手册导致的侵权问题的责任，包括可能侵犯第三方专利权的情况。用户在实施解决方案或产品时，可能需要第三方许可，并自行确保符合所有相关法律要求。 4. 保修与适用性：手册未提供任何形式的保证，包括针对特定应用的适配性。客户在使用过程中需自行承担风险。 5. 许可限制：文档不构成对Allwinner专利或其他知识产权的默示许可。如果需要实施解决方案或产品，可能需要获取额外的第三方许可。《Allwinner F1C200s User Manual v1.2》是一份关键的技术资料，为开发人员和系统集成者提供了关于F1C200s芯片的深入理解和操作指导，但在使用前必须确保遵循版权和法律要求，避免潜在的法律纠纷。这份手册对于理解芯片的功能特性、编程接口以及系统设计至关重要，但同时也提醒用户在实际应用中需谨慎处理和遵守相关规定。"

Table of Contents

4.2.5. Operation Mode ...................................................................................................................................... 146

4.2.5.1. Basic principle .............................................................................................................................. 146

4.2.5.2. Single-ended mode ...................................................................................................................... 146

4.2.5.3. Differential mode ......................................................................................................................... 147

4.2.5.4. Single touch detection ................................................................................................................. 147

4.2.5.5. Dual touch detection .................................................................................................................... 148

4.2.5.6. Touch pressure measurement ...................................................................................................... 148

4.2.5.7. Pen down detection, with programmable sensitivity .................................................................. 149

4.2.5.8. Median and averaging filter ......................................................................................................... 150

4.2.6. TP Register List ........................................................................................................................................ 151

4.2.7. TP Register Description ........................................................................................................................... 151

4.2.7.1. TP Control Register 0 .................................................................................................................... 151

4.2.7.2. TP Control Register 1 .................................................................................................................... 152

4.2.7.3. TP Control Register 2 .................................................................................................................... 153

4.2.7.4. TP Control Register 3 .................................................................................................................... 154

4.2.7.5. TP Interrupt FIFO Control Register ............................................................................................... 154

4.2.7.6. TP Interrupt FIFO Status Register ................................................................................................. 155

4.2.7.7. TP Common Data Register ............................................................................................................ 156

4.2.7.8. TP Data Register ........................................................................................................................... 156

4.3. Audio Codec ....................................................................................................................................................... 157

4.3.1. Overview ................................................................................................................................................. 157

4.3.2. Feature .................................................................................................................................................... 157

4.3.3. Block diagram .......................................................................................................................................... 157

4.3.4. Signal Description .................................................................................................................................... 157

Table of Contents

4.3.5. Power Description ................................................................................................................................... 158

4.3.6. Function Description ............................................................................................................................... 158

4.3.6.1. ADC ............................................................................................................................................... 158

4.3.6.2. Stereo ADC ................................................................................................................................... 158

4.3.6.3. Mixer ............................................................................................................................................ 158

4.3.6.4. Headphone Mixer ......................................................................................................................... 158

4.3.6.5. ADC Record Mixer ........................................................................................................................ 158

4.3.6.6. Analog Audio Input Path .............................................................................................................. 159

4.3.6.7. FM Input ....................................................................................................................................... 159

4.3.7. Audio Codec Register List ........................................................................................................................ 160

4.3.8. Audio Codec Register Description ........................................................................................................... 160

4.3.8.1. DAC Digital Part Control Register ................................................................................................. 160

4.3.8.2. DAC FIFO Control Register ............................................................................................................ 162

4.3.8.3. DAC FIFO Status Register .............................................................................................................. 164

4.3.8.4. DAC TX DATA Register ................................................................................................................... 164

4.3.8.5. ADC FIFO Control Register ............................................................................................................ 165

4.3.8.6. ADC FIFO Status Register .............................................................................................................. 166

4.3.8.7. ADC RX DATA Register .................................................................................................................. 167

4.3.8.8. DAC Analog & Output MIXER Control Register ............................................................................ 167

4.3.8.9. ADC Analog and Input mixer Control Register ............................................................................. 169

4.3.8.10. ADC&DAC performance tuning Register .................................................................................... 170

4.3.8.11. Bias & DA16 Calibration Control Register 0 ................................................................................ 171

4.3.8.12. Bias & DA16 Calibration Control Register 1 ................................................................................ 172

4.3.8.13. DAC TX Counter Register ............................................................................................................ 172

Table of Contents

4.3.8.14. ADC RX Counter Register ............................................................................................................ 172

4.3.8.15. DAC Debug Register ................................................................................................................... 172

4.3.8.16. ADC Debug Register ................................................................................................................... 173

4.3.8.17. ADC DAP Control Register .......................................................................................................... 173

4.3.8.18. ADC DAP Left Control Register ................................................................................................... 174

4.3.8.19. ADC DAP Right Control Register ................................................................................................. 175

4.3.8.20. ADC DAP Parameter Register ..................................................................................................... 176

4.3.8.21. ADC DAP Left Average Coef Register .......................................................................................... 177

4.3.8.22. ADC DAP Left Decay & Attack Time Register .............................................................................. 177

4.3.8.23. ADC DAP Right Average Coef Register ........................................................................................ 177

4.3.8.24. ADC DAP Right Decay & Attack Time Register ........................................................................... 178

4.3.8.25. ADC DAP HPF Coef Register ........................................................................................................ 178

4.3.8.26. ADC DAP Left Input Signal Low Average Coef Register .............................................................. 178

4.3.8.27. ADC DAP Right Input Signal Low Average Coef Register ............................................................ 178

4.3.8.28. ADC DAP Optimum Register ....................................................................................................... 179

Chapter 5. Display ............................................................................................................................................................. 180

5.1. TCON .................................................................................................................................................................. 181

5.1.1. Overview ................................................................................................................................................. 181

5.1.2. Feature .................................................................................................................................................... 181

5.1.3. Block Diagram ......................................................................................................................................... 181

5.1.3.1. LCD Timing Controller .................................................................................................................. 181

5.1.4. TCON Register List ................................................................................................................................... 182

5.1.5. TCON Register Description ...................................................................................................................... 183

5.1.5.1. TCON Control Register .................................................................................................................. 183

Table of Contents

5.1.5.2. TCON Interrupt Register 0 ............................................................................................................ 183

5.1.5.3. TCON Interrupt Register 1 ............................................................................................................ 184

5.1.5.4. TCON FRM Control Register ......................................................................................................... 184

5.1.5.5. TCON FRM Seed0 Red Register .................................................................................................... 184

5.1.5.6. TCON FRM Seed0 Green Register ................................................................................................. 184

5.1.5.7. TCON FRM Seed0 Blue Register ................................................................................................... 185

5.1.5.8. TCON FRM Seed1 Red Register .................................................................................................... 185

5.1.5.9. TCON FRM Seed1 Green Register ................................................................................................. 185

5.1.5.10. TCON FRM Seed1 Blue Register ................................................................................................. 185

5.1.5.11. TCON FRM Table Register 0 ........................................................................................................ 185

5.1.5.12. TCON FRM Table Register 1 ........................................................................................................ 185

5.1.5.13. TCON FRM Table Register 2 ........................................................................................................ 186

5.1.5.14. TCON FRM Table Register 3 ........................................................................................................ 186

5.1.5.15. TCON0 Control Register .............................................................................................................. 186

5.1.5.16. TCON Clock Control Register ...................................................................................................... 187

5.1.5.17. TCON0 Basic Timing Register 0 .................................................................................................. 187

5.1.5.18. TCON0 Basic Timing Register 1 .................................................................................................. 187

5.1.5.19. TCON0 Basic Timing Register 2 .................................................................................................. 188

5.1.5.20. TCON0 Basic Timing Register 3 .................................................................................................. 188

5.1.5.21. TCON0 HV Timing Register ......................................................................................................... 188

5.1.5.22. TCON0 CPU Interface Control Register ....................................................................................... 189

5.1.5.23. TCON0 CPU Write Register ......................................................................................................... 190

5.1.5.24. TCON0 CPU Read Register .......................................................................................................... 190

5.1.5.25. TCON0 CPU Read NX Register .................................................................................................... 190

Table of Contents

5.1.5.26. TCON0 IO Control Register 0 ...................................................................................................... 190

5.1.5.27. TCON0 IO Control Register 1 ...................................................................................................... 191

5.1.5.28. TCON1 Control Register .............................................................................................................. 191

5.1.5.29. TCON1 Basic Timing Register 0 .................................................................................................. 192

5.1.5.30. TCON1 Basic Timing Register 1 .................................................................................................. 192

5.1.5.31. TCON1 Basic Timing Register 2 .................................................................................................. 192

5.1.5.32. TCON1 Basic Timing Register 3 .................................................................................................. 193

5.1.5.33. TCON1 Basic Timing Register 4 .................................................................................................. 193

5.1.5.34. TCON1 Basic Timing Register 5 .................................................................................................. 193

5.1.5.35. TCON1 IO Control Register 0 ...................................................................................................... 193

5.1.5.36. TCON1 IO Control Register 1 ...................................................................................................... 194

5.1.5.37. TCON Debug Information Register ............................................................................................. 194

5.2. Display Engine Front-End ................................................................................................................................... 196

5.2.1. Overview ................................................................................................................................................. 196

5.2.2. Feature .................................................................................................................................................... 196

5.2.3. Block Diagram ......................................................................................................................................... 196

5.2.4. DEFE Register List .................................................................................................................................... 196

5.2.5. DEFE Register Description ....................................................................................................................... 198

5.2.5.1. DEFE Module Enable Register ...................................................................................................... 198

5.2.5.2. DEFE Frame Process Control Register .......................................................................................... 198

5.2.5.3. DEFE CSC Bypass Register ............................................................................................................. 199

5.2.5.4. DEFE Algorithm Selection Register ............................................................................................... 200

5.2.5.5. DEFE Line Interrupt Conrtol Register............................................................................................ 200

5.2.5.6. DEFE Input Channel 0 Buffer Address Register ............................................................................ 200

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