STM32F100RB：低中密度ARM Cortex-M3 MCU datasheet详解

需积分: 9 61 浏览量更新于2024-07-24 收藏 1.17MB PDF 举报

STM32F100RB是一款由STMicroelectronics生产的低密度和中密度值线高级ARM架构的32位微控制器，它针对的是性能需求适中的应用。该芯片主要特性包括： 1. **处理器核心**: STM32F100系列采用ARM Cortex-M3内核，其最高工作频率可达24MHz，具有1.25 DMIPS/MHz的Dhrystone 2.1基准性能，支持单周期乘法和硬件除法，提供高效能计算能力。 2. **内存配置**: 芯片内置16至128 KB的闪存，以及4至8 KB的静态随机访问存储器（SRAM），能满足不同项目对存储容量的需求。 3. **时钟、复位与供电管理**: 支持2.0到3.6伏的宽电压范围，适用于各种应用环境。集成有电源管理单元，包括上电复位(POR)、掉电复位(PDR)和可编程电压检测器(PVD)。内置8 MHz工厂预调谐的晶体振荡器，以及40 kHz内部RC振荡器，同时还有一个用于CPU时钟的锁相环 PLL。此外，还提供了32 kHz时钟供RTC（实时时钟）使用，具有自校准功能。 4. **低功耗设计**: STM32F100RB支持多种低功耗模式，如睡眠、停机和待机状态，配合电池备份电压(VBAT)，延长设备在有限电池下的续航时间。 5. **调试接口**: 提供串行 Wire Debug (SWD) 和 JTAG 接口，方便开发过程中进行程序下载、调试和故障排查。 6. **DMA控制器**: 内置7通道直接内存访问(DMA)控制器，可以有效地管理和加速外设间的数据传输，支持定时器、ADC、SPI、I2C、USART和DAC等多种外设。 7. **模拟信号处理**: 配备1个12位，转换时间仅为1.2 µs的A/D转换器，最多支持16通道，能够测量0到3.6伏的电压范围，并具备温度传感器功能。另外还有2个12位D/A转换器，支持模拟信号的生成。 8. **高速I/O**: 提供多达80个高速输入/输出引脚，适合构建高数据速率接口和信号处理电路。 STM32F100RB凭借其高性能、丰富的内存选项、灵活的供电和时钟管理、低功耗特性和强大的调试能力，是一款适合多种工业控制、消费电子和物联网应用的理想选择。开发者可以根据具体项目需求，利用其丰富的功能实现高效能、低功耗的设计解决方案。

Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

14/86 Doc ID 16455 Rev 5

2.2 Overview

2.2.1 ARM

Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F100xx value line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

2.3 Embedded Flash memory

Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.

2.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.5 Embedded SRAM

Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description

Doc ID 16455 Rev 5 15/86

2.6 Nested vectored interrupt controller (NVIC)

The STM32F100xx value line embeds a nested vectored interrupt controller able to handle

up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)

and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.7 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 18 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.8 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 24 MHz.

2.9 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash

● Boot from system memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

16/86 Doc ID 16455 Rev 5

2.10 Power supply schemes

● V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through V

pins.

● V

SSA

, V

DDA

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC is used).

DDA

and V

SSA

must be connected to V

and V

, respectively.

● V

BAT

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

2.11 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

2.12 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop mode

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.13 Low-power modes

The STM32F100xx value line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description

Doc ID 16455 Rev 5 17/86

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.14 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, DAC, I

C, USART, all timers and

ADC.

2.15 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit

registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC

features a 32-bit programmable counter for long term measurement using the Compare

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.16 Timers and watchdogs

The STM32F100xx devices include an advanced-control timer, six general-purpose timers,

two basic timers and two watchdog timers.

Table 3 compares the features of the advanced-control, general-purpose and basic timers.

剩余85页未读，继续阅读

zhangcongwwee

粉丝: 0
资源: 1

STM32F100RB：低中密度ARM Cortex-M3 MCU datasheet详解

STM32说明 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB )

STM32F100RB_sch.zip_CAN 原理图_ST_i/v 原理图_st link_swd

STM32F100RB开发板电路设计原理图下载

STM32f100_rtc.rar_stm32f100

stm32f10x_stdperiph_lib.zip_CEC_stm32f100_stm32f100 lib_stm32f10

STM32f100xx.rar_STM32F100xx_comm

7190_deneme.rar_7190_AD7190_Tested_stm32f100_stm32f100 uart

LoRa_STM32F100_Sx1276.rar_keil_lora_stm32f100_sx1276

stm32f100cb

STM32F100 手册

最新资源