Tessent MemoryBIST用户手册（2020.3版，带书签）

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本资源为"Tessent® MemoryBIST用户手册"，适用于Tessent Shell软件版本2020.3，文档修订至第18版。这是一份未经公开的工作文档，由Siemens Industry Software Inc.及其关联公司 Mentor Graphics Corporation 所拥有，包含了关于内存自测试（Memory Built-in Self-Test，MBIST）的重要技术细节。 MBIST是现代集成电路设计中的关键组成部分，用于在芯片制造过程中对存储器单元进行定期检查，确保其正确性和一致性。该手册详细介绍了如何利用Tessent Shell软件来实施和管理内存测试流程，包括但不限于配置、执行、分析和报告内存测试结果。它涵盖了MBIST的基本原理、测试方法、常见故障检测以及高级调试策略。由于版权原因，用户只能在内部业务环境中复制此文档，且必须完整保留版权声明和保密条款。Siemens保留在任何时候更改文档中所包含规格和其他信息的权利，因此读者在使用时应与Siemens确认是否有任何更新或变动。此外，购买和许可Siemens产品的条件是在Siemens与其客户之间签订的书面协议中规定的，最终用户需要遵守这些条款和条件。这份手册提供了重要的参考信息，帮助工程师们优化内存测试流程，确保产品的质量和可靠性，对于从事嵌入式系统、半导体制造或电子设计验证的专业人士来说，是一份不可或缺的技术指南。

List of Figures

Tessent® MemoryBIST User’s Manual, v2020.3

Figure 5-18. Repair Support in Memory Library File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 5-19. Example Memory with Two Spare Rows Using Parallel BISR interface . . . . 190

Figure 5-20. Memory Library File Fragment for Two Spare Rows Using Parallel BISR Interface

191

Figure 5-21. Example Memory With One Spare Column and Serial BISR Interface. . . . . . 192

Figure 5-22. A Fragment of the Memory Library File Sample Syntax . . . . . . . . . . . . . . . . . 193

Figure 5-23. BISR Controller Fuse Box Read Access Protocol . . . . . . . . . . . . . . . . . . . . . . 203

Figure 5-24. BISR Controller Fuse Box Write Access Protocol . . . . . . . . . . . . . . . . . . . . . . 204

Figure 5-25. BISR Controller Fuse Box Transfer and Program Protocol . . . . . . . . . . . . . . . 204

Figure 5-26. Sample Generic Fuse Box Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 5-27. Example MBISR TCD File Reporting BISR Statistics . . . . . . . . . . . . . . . . . . 213

Figure 5-28. Example PatternsSpecification to Verify BIRA and BISR. . . . . . . . . . . . . . . . 226

Figure 5-29. Example PatternsSpecification Configuration for FuseBox Access Mode. . . . 230

Figure 5-30. PatternsSpecification Configuration for Autonomous Modes . . . . . . . . . . . . . 231

Figure 5-31. PatternsSpecification Configuration for Autonomous Modes for MemoryBIST-

Only Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 5-32. BISR Controller Protocol in Functional Mode (Single Power Domain Group) 235

Figure 5-33. BISR Controller Protocol in Functional Mode (Multiple Power Domain Groups)

237

Figure 5-34. BISR Controlled from Functional Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 5-35. Post-Repair MemoryBIST with BISR Controlled from Functional Inputs . . . 242

Figure 5-36. iProc Usage for Physical Block Level With No Fuse Box Controller . . . . . . . 243

Figure 5-37. iProc Usage for Chip Level With Fuse Box Controller Present . . . . . . . . . . . . 243

Figure 5-38. BISR Manufacturing Flow Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 5-39. Initialization Test Pattern Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 5-40. Pre-Repair Test Patterns Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 5-41. Example Configuration for TP2_1 Repair Test Patterns . . . . . . . . . . . . . . . . . 249

Figure 5-42. Example Configuration for TP2_2 Repair Test Patterns . . . . . . . . . . . . . . . . . 250

Figure 5-43. Example Configuration for Post-Repair Test Patterns . . . . . . . . . . . . . . . . . . . 252

Figure 5-44. Flow Variation: Testing Repair Solution Before Fuse Programming. . . . . . . . 254

Figure 5-45. Flow Variation: Performing Fuse Programming During Any Test Insertion . . 255

Figure 5-46. Fuse Box Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 5-47. Fuse Box Organization (max_fuse_box_programming_sessions > 1) . . . . . . . 258

Figure 5-48. Encoding of Repair Information Using CompressBisrChain Script. . . . . . . . . 259

Figure 5-49. Manufacturing Flow Using CompressBisrChain Script (Incremental Repair). 261

Figure 5-50. Soft Incremental Repair Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 5-51. BISR-to-BIRA Transfer Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 5-52. Detection of Repair Needed Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 5-53. Hard Incremental Repair Manufacturing Flow Example for

max_fuse_box_programming_sessions: <integer> . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 5-54. Hard Incremental Repair Manufacturing Flow Example for

max_fuse_box_programming_sessions: unlimited . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 5-55. Incompatible Address Mapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 5-56. Incompatible Segment Size Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 5-57. DefaultsSpecification Repair Sharing Properties . . . . . . . . . . . . . . . . . . . . . . . 283

List of Figures

Tessent® MemoryBIST User’s Manual, v2020.3

Figure 5-58. Repair Sharing on All Memory Instances Example . . . . . . . . . . . . . . . . . . . . . 283

Figure 5-59. Example DftSpecification Properties for Repair Sharing . . . . . . . . . . . . . . . . . 285

Figure 5-60. BISR Chain Ordering with Repair Sharing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 5-61. BISR Register Location with Local Comparators . . . . . . . . . . . . . . . . . . . . . . 287

Figure 5-62. BISR Register Location Example with Two Repair Groups . . . . . . . . . . . . . . 288

Figure 5-63. BISR Register Location Example with One Repair Group . . . . . . . . . . . . . . . 288

Figure 5-64. Overall Fast BISR Loading Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 5-65. Parallel Load Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 6-1. Example of CHIP with a Shared Bus Memory Cluster Module . . . . . . . . . . . . . 301

Figure 6-2. Composition of Logical Memory LM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 6-3. Shared Bus Memory Cluster Module After Embedded Test Insertion. . . . . . . . 303

Figure 6-4. Memory BIST Shared Bus Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 6-5. Memory Cluster TCD Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 6-6. Logical Memory TCD Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 6-7. Example Logical Memory with Four Physical Memories . . . . . . . . . . . . . . . . . 309

Figure 6-8. Design Overview of a Memory Cluster Module with BISR. . . . . . . . . . . . . . . . 323

Figure 6-9. Four Physical Memories with Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 6-10. Logical Memory Placed Outside of a Shared Bus Memory Cluster. . . . . . . . . 326

Figure 6-11. Memory Cluster with Two Shared Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . 329

Figure 6-12. Modeling a Memory Cluster with Two Shared Bus Interfaces. . . . . . . . . . . . . 330

Figure 7-1. Simple Algorithm Writing and Reading all Memory Locations. . . . . . . . . . . . . 338

Figure 7-2. Example Operation Set Using row_address_count_enable and

column_address_count_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 7-3. Fast Diagonal Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 7-4. Fast Diagonal Operation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Figure 7-5. Example Usage for the switch_address_register Property . . . . . . . . . . . . . . . . . 345

Figure 7-6. Example illustrating the use of invert_expect_data . . . . . . . . . . . . . . . . . . . . . . 346

Figure 7-7. Example Illustrating the use of invert_write_data . . . . . . . . . . . . . . . . . . . . . . . 348

Figure 7-8. Fast Test Sequence with Simple Data Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 7-9. Portion of syncWRvcd Library Operation Set . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Figure 7-10. Pseudo Concurrent Write Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 7-11. Combining Pseudo Concurrent Write and Concurrent Write Operations Example

370

Figure 7-12. Example Operation with Write and Concurrent Read to the Same Address . . 371

Figure 7-13. Example Operation with Write and Concurrent Write to the Same Address . . 372

Figure 8-1. Scan-based Diagnosis Approach Topology Using Enhanced Stop-On-Nth-Error

Serial Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 9-1. Hierarchical Design Example with Many Memories . . . . . . . . . . . . . . . . . . . . . 394

Figure 9-2. Hierarchical Design Example with MemoryBIST Controllers. . . . . . . . . . . . . . 395

Figure 9-3. Steps to Implement MemoryBIST for Example Design in One Tool Invocation 397

Figure A-1. Memory with 2 Stages of Built-In Pipelining on the Output Data . . . . . . . . . . 416

Figure C-1. LVMarchX Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Figure C-2. LVMarchY Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Figure C-3. LVMarchCMinus Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . 636

Figure C-4. LVMarchLA Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

List of Figures

Tessent® MemoryBIST User’s Manual, v2020.3

Figure C-5. LVRowBar Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure C-6. LVColumnBar Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Figure C-7. LVGalPat Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure C-8. LVGalColumn Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure C-9. LVGalRow Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Figure C-10. LVCheckerboard1X1 Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . 678

Figure C-11. LVCheckerboard4X4 Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . 683

Figure C-12. LVWalkingPat Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . 689

Figure C-13. LVBitSurroundDisturb Example Algorithm Wrapper . . . . . . . . . . . . . . . . . . . 703

Figure E-1. Parallel Static Retention Test Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Figure E-2. Parallel Static Retention Test with Controller Groups . . . . . . . . . . . . . . . . . . . . 727

Figure F-1. Simple Architecture for the Memory in Example 1 . . . . . . . . . . . . . . . . . . . . . . 731

Figure F-2. Logical Memory Cell Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

Figure F-3. Row Address Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

Figure F-4. Column Address Mapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

Figure F-5. Data Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

Figure F-6. Data Mapping Example that Incorporates AND. . . . . . . . . . . . . . . . . . . . . . . . . 742

Figure G-1. Example Memory with Parallel BISR Interface . . . . . . . . . . . . . . . . . . . . . . . . 746

Figure G-2. Memory Library File Sample Syntax for Parallel BISR Interface. . . . . . . . . . . 747

Figure G-3. Example Memory with Serial BISR Interface . . . . . . . . . . . . . . . . . . . . . . . . . 752

Figure G-4. Memory Library File Sample Syntax for Serial BISR Interface . . . . . . . . . . . . 752

Figure H-1. Example Read Algorithm for a Single Location . . . . . . . . . . . . . . . . . . . . . . . . 759

Figure H-2. Example Write Algorithm for a Block of Locations . . . . . . . . . . . . . . . . . . . . . 761

Figure H-3. Test Steps Used for Verification of Debug Capability . . . . . . . . . . . . . . . . . . . 763

Figure H-4. Functional Debug Mode Write Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Figure H-5. Functional Debug Mode Read Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Figure I-1. Advanced BAP Memory Access Diagram (single sequencer) . . . . . . . . . . . . . . 771

Figure I-2. Advanced BAP Memory Access Diagram (multiple sequencers). . . . . . . . . . . . 773

Figure I-3. Advanced BAP Shared Bus Access Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

Figure I-4. BAP Direct Access Interface Timing Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 783

Figure I-5. BAP Direct Access Interface Timing Protocol with Multiple Sequencers . . . . . 785

Figure I-6. Example BAP Direct Access Parallel Retention Test . . . . . . . . . . . . . . . . . . . . . 803

Tessent® MemoryBIST User’s Manual, v2020.3

List of Tables

Table 3-1. Parameter Impact on Performance and Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 5-1. BIRA Module Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 5-2. Fuse Box for Mapping Defective IO/Columns . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 5-3. <MEMORY_INSTANCE_NAME>_REPAIR_STATUS Decodes . . . . . . . . . . 157

Table 5-4. <MEMORY_INSTANCE_NAME>_REPAIR_STATUS Decodes . . . . . . . . . . 168

Table 5-5. <MemoryInstance>_STATUS_REG Decodes . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 5-6. Fuse Box Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 5-7. REPAIR_STATUS Register Decodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 5-8. GO Output Interpretation by Repair Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 5-9. Action Table for GO_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Table 5-10. Action Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 5-11. GO_ID Behavior in BIRA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 5-12. GO_ID Behavior in Stop-On-Error Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 5-13. GO_ID Behavior in Go/NoGo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 5-14. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 5-15. Fast BISR Loading Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 5-16. BISR Loading Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 6-1. Shared Bus MemoryInstanceName Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table A-1. Conventions for Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table A-2. Syntax Conventions for Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table A-3. Valid Function Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Table A-4. Function Value Details and Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Table A-5. Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Table A-6. Example TDR Configurations Using tessent_enable_group and

tessent_common_tdr_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Table A-7. Valid Port Function Values for Shared Bus Memory Cluster TCD . . . . . . . . . . 470

Table A-8. Valid Port Function Values Unique to the Shared Bus Memory Cluster TCD Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Table B-1. Configuration Data Editing and Introspection Commands . . . . . . . . . . . . . . . . 491

Table B-2. Syntax Conventions for Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Table B-3. Un-Nested address_sequence Property Modification . . . . . . . . . . . . . . . . . . . . . 548

Table B-4. Nested address_sequence Property Modification . . . . . . . . . . . . . . . . . . . . . . . . 548

Table B-5. Un-Nested expect_data_sequence Property Modification . . . . . . . . . . . . . . . . . 550

Table B-6. Nested expect_data_sequence Property Modification . . . . . . . . . . . . . . . . . . . . 551

Table B-7. Un-Nested write_data_sequence Property Modification . . . . . . . . . . . . . . . . . . 555

Table B-8. Nested write_data_sequence Property Modification . . . . . . . . . . . . . . . . . . . . . 555

Table B-9. Required Settings for Increment/Decrement by 1 . . . . . . . . . . . . . . . . . . . . . . . 574

Table B-10. Required Settings for Increment/Decrement by > 1 . . . . . . . . . . . . . . . . . . . . . 575

Table B-11. Required Settings for Increment/Decrement by 1 . . . . . . . . . . . . . . . . . . . . . . 577

Table B-12. Required Settings for Increment/Decrement by > 1 . . . . . . . . . . . . . . . . . . . . . 578

List of Tables

Tessent® MemoryBIST User’s Manual, v2020.3

Table B-13. write _enable Write Access Operation When Explicitly Specified . . . . . . . . . 586

Table B-14. write_enable Write Access Operation Default Settings . . . . . . . . . . . . . . . . . . 587

Table C-1. MemoryBIST Algorithm Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Table C-2. MemoryBist Algorithm Test Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Table C-3. MemoryBist Algorithm PSRT Test Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Table C-4. Description of SMarch Test Algorithm per Test Port . . . . . . . . . . . . . . . . . . . . 599

Table C-5. Description of ReadOnly Test Algorithm per Test Port . . . . . . . . . . . . . . . . . . . 601

Table C-6. Description of SMarchCHKB Test Algorithm per Test Port . . . . . . . . . . . . . . . 602

Table C-7. Description of SMarchCHKBci Test Algorithm per Test Port . . . . . . . . . . . . . 605

Table C-8. Description of SMarchCHKBcil Test Algorithm per Test Port . . . . . . . . . . . . . 608

Table C-9. Description of SMarchCHKBvcd Test Algorithm per Test Port . . . . . . . . . . . . 613

Table C-10. Mapping of Operation Code to Operation Name . . . . . . . . . . . . . . . . . . . . . . . 622

Table C-11. Description of LVMarchX Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table C-12. Description of LVMarchY Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Table C-13. Description of LVMarchCMinus Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 634

Table C-14. Description of LVMarchLA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table C-15. Description of LVRowBar Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Table C-16. Description of LVColumnBar Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Table C-17. Description of LVGalPat Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Table C-18. Description of LVGalColumn Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Table C-19. Description of LVGalRow Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Table C-20. Description of LVCheckerboard1X1 Algorithm . . . . . . . . . . . . . . . . . . . . . . . 676

Table C-21. Description of LVCheckerboard4X4 Algorithm . . . . . . . . . . . . . . . . . . . . . . . 681

Table C-22. Description of LVWalkingPat Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Table C-23. Description of LVBitSurroundDisturb Algorithm . . . . . . . . . . . . . . . . . . . . . . 692

Table I-1. BAP Direct Access Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

Table I-2. Pattern Generation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

Table I-3. Retention Test Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

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