dsPIC33FJ32MC202/204与dsPIC33FJ16MC304：16位数字信号控制器详解

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本文档是关于Microchip Technology Inc.生产的两款数字信号控制器——dsPIC33FJ32MC202/204和dsPIC33FJ16MC304的数据手册（DS70283K）。这些控制器采用16位dsPIC33FC CPU架构，具备出色的性能和节能特性。首先，关于CPU核心，16位dsPIC33FC处理器提供了高效能代码执行能力，包括C和Assembly语言的优化支持。其硬件特性显著，拥有两个40位宽的累加器，可以实现单周期内完成MAC（乘法累加）和MPY（乘法）运算，且具备双数据预取功能，进一步提升计算速度。此外，还内置了单周期混合精度乘法硬件除法，增强了数学运算能力。在时钟管理方面，控制器内置2%精度的内部振荡器，以及可编程的PLL（锁相环路）和时钟源选择，确保了灵活的时钟配置。FSCM（Fail-Safe Clock Monitor）提供故障检测，而独立的看门狗定时器（WDT）用于系统稳定性监控。此外，这些设备支持快速唤醒和启动模式，以减少功耗。在低功耗设计上，控制器支持多种管理模式，如Sleep、Idle和Doze状态，能够在不同应用中显著节省电能。集成的电源复位和棕色-out复位功能保证了系统的可靠启动。典型情况下，动态电流仅为1.35mA/MHz，而进入休眠模式下的IPD（Idle Power Drain）电流低至55μA，实现了极低的功耗。高精度PWM模块是这些控制器的一大亮点，支持多达四路独立定时的PWM信号发生，每路支持上升和下降边的死区时间设置，确保输出的精确控制。分辨率高达12.5ns，适用于广泛的应用场景，如DC/DC转换、AC/DC转换、逆变器、PFC（功率因数校正）、照明、BLDC（永磁同步电机）、PMSM（永磁同步电机）、ACIM（交流感应电机）和SRM（同步 reluctance motor）等。此外，文档还提及了高级的模拟功能，其中包括可配置为10位或1.1位分辨率的ADC模块，能够根据需求调整精度，同时支持灵活的触发配置，便于与ADC转换配合使用。内置的可编程故障输入功能则增加了系统故障检测和处理的灵活性。 dsPIC33FJ32MC202/204和dsPIC33FJ16MC304是高性能的数字信号控制器，集成了丰富的功能，适用于对低功耗、高速度和高精度控制有高要求的工业和消费电子应用。通过理解并利用这些特性，开发人员能够构建出高效能、可靠的嵌入式系统解决方案。

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

2.7 Oscillator Value Conditions on

Device Start-up

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

to ≤ 8 MHz for start-up with PLL enabled. This means

that if the external oscillator frequency is outside this

range, the application must start-up in FRC mode first.

The default PLL settings after a POR with an oscillator

frequency outside this range will violate the device

operating speed.

Once the device powers up, the application firmware

can initialize the PLL SFRs, CLKDIV and PLLDBF to a

suitable value, and then perform a clock switch to the

Oscillator + PLL clock source. Note that clock switching

must be enabled in the device Configuration word.

2.8 Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™

in-circuit emulator is selected as a debugger, it auto-

matically initializes all of the A/D input pins (ANx) as

“digital” pins, by setting all bits in the AD1PCFGL regis-

ter.

The bits in the registers that correspond to the A/D pins

that are initialized by MPLAB ICD 3 or MPLAB REAL

ICE™ in-circuit emulator, must not be cleared by the

user application firmware; otherwise, communication

errors will result between the debugger and the device.

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must clear the corresponding bits in the

AD1PCFGL register during initialization of the ADC

module.

When MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit

emulator is used as a programmer, the user application

firmware must correctly configure the AD1PCFGL

done during debugger operation. Failure to correctly

configure the register(s) will result in all A/D pins being

recognized as analog input pins, resulting in the port

value being read as a logic ‘0’, which may affect user

application functionality.

2.9 Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between V

and the unused pins.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

3.0 CPU

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

CPU module has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set, including

significant support for DSP. The CPU has a 24-bit

instruction word with a variable length opcode field. The

Program Counter (PC) is 23 bits wide and addresses up

to 4M x 24 bits of user program memory space. The

actual amount of program memory implemented varies

by device. A single-cycle instruction prefetch mechanism

is used to help maintain throughput and provides

predictable execution. All instructions execute in a single

cycle, with the exception of instructions that change the

program flow, the double-word move (MOV.D) instruction

and the table instructions. Overhead-free program loop

constructs are supported using the DO and REPEAT

instructions, both of which are interruptible at any point.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

devices have sixteen, 16-bit working registers in the

programmer’s model. Each of the working registers can

serve as a data, address or address offset register. The

16th working register (W15) operates as a software Stack

Pointer (SP) for interrupts and calls.

There are two classes of instruction in the

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

devices: MCU and DSP. These two instruction classes

are seamlessly integrated into a single CPU. The

instruction set includes many addressing modes and is

designed for optimum C compiler efficiency. For most

instructions, the dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 is capable of executing a data (or

program data) memory read, a working register (data)

read, a data memory write and a program (instruction)

memory read per instruction cycle. As a result, three

parameter instructions can be supported, allowing

A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1, and

the programmer’s model for the

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is

shown in Figure 3-2.

3.1 Data Addressing Overview

The data space can be addressed as 32K words or

64 Kbytes and is split into two blocks, referred to as X

and Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The

MCU class of instructions operates solely through the

X memory AGU, which accesses the entire memory

map as one linear data space. Certain DSP instructions

operate through the X and Y AGUs to support dual

operand reads, which splits the data address space

into two parts. The X and Y data space boundary is

device-specific.

Overhead-free circular buffers (Modulo Addressing

mode) are supported in both X and Y address spaces.

The Modulo Addressing removes the software

boundary checking overhead for DSP algorithms.

Furthermore, the X AGU circular addressing can be

used with any of the MCU class of instructions. The X

AGU also supports Bit-Reversed Addressing to greatly

simplify input or output data reordering for radix-2 FFT

algorithms.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K program word boundary defined by the 8-bit

Program Space Visibility Page register (PSVPAG). The

program-to-data-space mapping feature lets any

instruction access program space as if it were data

space.

3.2 DSP Engine Overview

The DSP engine features a high-speed 17-bit by 17-bit

multiplier, a 40-bit ALU, two 40-bit saturating

accumulators and a 40-bit bidirectional barrel shifter.

The barrel shifter is capable of shifting a 40-bit value up

to 16 bits right or left, in a single cycle. The DSP

instructions operate seamlessly with all other

instructions and have been designed for optimal

real-time performance. The MAC instruction and other

associated instructions can concurrently fetch two data

operands from memory while multiplying two W

registers and accumulating and optionally saturating

the result in the same cycle. This instruction

functionality requires that the RAM data space be split

for these instructions and linear for all others. Data

space partitioning is achieved in a transparent and

flexible manner through dedicating certain working

registers to each address space.

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 family of devices. It

is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to

Section 2. “CPU” (DS70204) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

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dsPIC33FJ32MC202/204与dsPIC33FJ16MC304：16位数字信号控制器详解

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