TI Cortex-M4微控制器实战教程：ARM技术指南

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"《Practical Microcontroller Engineering with ARM Technology》是一本由IEEE Press出版的专业书籍，旨在提供深入浅出的ARM Cortex-M4微控制器工程实践指南。该书以德州仪器（TI）的微控制器作为核心教学平台，着重于嵌入式系统设计和开发，特别是基于ARM技术的应用。作者 Ying Bai 来自约翰逊·史密斯大学计算机科学与工程系，确保了内容的理论性和实用性相结合。书中涵盖了诸如硬件接口、软件编程、实时操作系统(RTOS)、电源管理、通信协议以及低功耗设计等关键主题，适合电子工程、计算机科学以及嵌入式系统领域的学生和工程师使用。通过本书，读者将学习到如何利用ARM Cortex-M4单片机实现高效能、低功耗的解决方案，并理解其在物联网(IoT)、工业自动化、消费电子产品等领域的广泛应用。此外，这本书还强调了与实际项目相关的案例研究和实验，帮助读者将理论知识转化为实际操作技能。同时，它遵循严格的版权规定，确保知识产权的尊重，只在获得IEEE出版社或相关法律规定许可的情况下进行复制或传播。《Practical Microcontroller Engineering with ARM Technology》是一本实用且权威的教材，为微控制器工程人员提供了全面的ARM技术学习和实践经验，对于提升嵌入式系统开发人员的专业素养具有重要意义。"

7.5.4.1 Voltage Reference and Resolutions 471

7.5.4.2 Differential Input Mode 471

7.5.4.3 Internal Temperature Sensor 472

7.5.5 Initialization and Conﬁguration 473

7.5.5.1 ADC-Related GPIO Ports Initialization 473

7.5.5.2 ADC Module Initialization 474

7.5.5.3 Sample Sequencers Initialization 474

7.5.6 Build the Analog-to-Digital Converter Programming Project 475

7.5.6.1 ADC Module in EduBASE ARM



Trainer 475

7.5.6.2 Create the ADC Programming Project (Polling-Driven) 476

7.5.6.3 Create the Source File DRAADCPoll.c 476

7.5.6.4 Set Up the Environment to Build and Run the Project 479

7.5.7 ADC Module API Functions Provided in the TivaWare

Peripheral Driver

Library 480

7.5.7.1 Conﬁguring and Handling the Sample Sequencers API Functions 481

7.5.7.2 Conﬁguring and Controlling the Processor Trigger API Functions 481

7.5.7.3 Conﬁguring and Processing the ADC Interrupt API Functions 483

7.5.7.4 Build an Example ADC Project Using API Functions 484

7.6 PWM-Controlled DC and Step Motors Programming Project 486

7.6.1 The PWM Principle and Implementations 487

7.6.2 PWM Modules in the TM4C123GH6PM MCU System 487

7.6.2.1 The PWM Generator Block 488

7.6.2.1.1 The PWM Counter (Timer) 488

7.6.2.1.2 The PWM Comparators 488

7.6.2.1.3 The PWM Output Signals Generator 489

7.6.2.1.4 The Dead-Band Generator 490

7.6.3 PWM Generator Functional Block Diagram 490

7.6.3.1 PWM Generator Block Control Register (

PWMnCTL) 491

7.6.3.2 PWM Generator Block Load Register (PWMnLOAD) 493

7.6.3.3 PWM Generator Block Count Register (PWMnCOUNT) 493

7.6.3.4 PWM Generator Block Comparator A Register (PWMnCMPA) 493

7.6.3.5 PWM Generator Block Comparator B Register (PWMnCMPB) 494

7.6.3.6 PWM Generator A Register (PWMnGENA) 494

7.6.3.7 PWM Generator B Register (PWMnGENB) 495

7.6.3.8 PWM Generator Dead-Band Control Register (PWMnDBCTL) 496

7.6.3.9 PWM Generator Dead-Band Rising-Edge Delay Register

(PWMnDBRISE) 497

7.6.3.10 PWM Generator Dead-Band Falling-Edge Delay Register

(PWMnDBFALL) 497

7.6.3.11 PWM Interrupt and Trigger Enable Register (PWMnINTEN) 498

7.6.3.12 PWM Raw Interrupt Status Register (PWMnRIS) 498

7.6.3.13 PWM Interrupt Status and Clear Register (PWMnISC) 499

7.6.3.14 PWM Fault Source n Register (PWMFLTSRCn) 501

7.6.4 PWM Module Architecture and Functional Block Diagram 502

7.6.4.1 The Control and Status Block 503

7.6.4.1.1 The Run-Mode Clock Conﬁguration Register (RCC) 504

7.6.4.1.2 The PWM Master Control Register (PWMCTL) 504

xvi Contents

7.6.4.1.3 The PWM Timer Base Synchronous Register (PWMSYNC) 504

7.6.4.1.4 The PWM Status Register (PWMSTATUS) 505

7.6.4.1.5 The PWM Peripheral Properties Register (PWMPP) 505

7.6.4.2 The Output Control Block 505

7.6.4.2.1 The PWM Output Enable Register (PWMENABLE) 505

7.6.4.2.2 The PWM Output Inversion Register (PWMINVERT) 506

7.6.4.2.3 The PWM Output Fault Register (PWMFAULT) 506

7.6.4.2.4 The PWM Fault Condition ValueRegister (PWMFAULTVAL)

507

7.6.4.2.5 The PWM Enable Update Register (PWMENUPD) 507

7.6.4.3 The Interrupt Control Block 507

7.6.4.3.1 The PWM Interrupt Enable Register (PWMINTEN) 508

7.6.4.3.2 The PWM Raw Interrupt Status Register (PWMRIS) 509

7.6.4.3.3 The PWM Interrupt Status and Clear Register (PWMISC) 509

7.6.5 PWM Module Components and Signal Descriptions 509

7.6.5.1 PWM Signal Description 510

7.6.5.2 Synchronization Methods 511

7.6.5.3 Fault Conditions 512

7.6.6 PWM Module Initialization and Conﬁguration 513

7.6.6.1 Initialize and Conﬁgure the Clock Source for PWM Module and GPIO

Ports 513

7.6.6.2 Initialize and Conﬁgure GPIO Ports and Pins Related to PWM

Modules 513

7.6.6.3 Initialize and Conﬁgure the PWM Module and Generators 514

7.6.7 PWM Module Architecture in the EduBASE ARM



Trainer 515

7.6.8 Build an Example PWM Programming Project 516

7.6.8.1 Create a PWM Application Project DRAPWM 517

7.6.8.2 Set Up the Environment to Build and Run the Project 520

7.7 The PWM API Functions in the TivaWare

Peripheral Driver Library 521

7.7.1 PWM Modules and Generators Conﬁguration and Set Up Control

Functions 521

7.7.2 PWM Output Control Functions 523

7.7.3 PWM Interrupt and Fault Control Functions 523

7.8 Chapter Summary 525

Homework 527

Chapter 8 ARM



Cortex



-M4 Serial I/O Ports Programming 547

8.1 Overview and Introduction 547

8.2 GPIO Module Architecture and GPIO Port Conﬁguration 548

8.3 Synchronous Serial Interface (SSI) 551

8.3.1 Asynchronous and Synchronous Communication Protocols and Data

Framing 552

8.3.2 Synchronous Serial Interface Architecture and Functional Block Diagram 555

8.3.3 The Synchronous Data Transmission Format and Frame 556

8.3.3.1 Texas Instruments

Synchronous Serial Frame 558

8.3.3.2 Freescale SPI Frame 558

Contents xvii

8.3.3.3 MICROWIRE Frame 559

8.3.4 SSI Module Components and Signal Descriptions 560

8.3.4.1 SSI Control Signals and GPIO SSI Control Registers 560

8.3.4.2 SSI Module Bit Rate Generation and Clock Control 562

8.3.4.3 SSI Module Control/Status and FIFO Control 564

8.3.4.3.1 SSI Control 1 Register (SSICR1) 564

8.3.4.3.2 SSI Status Register (SSISR) 565

8.3.4.3.3 SSI Data Register (SSIDR) 565

8.3.4.3.4 FIFO Operations 566

8.3.4.4 SSI Module Interrupt and DMA Control 567

8.3.4.4.1 SSI Interrupt Mask Register (SSIIM) 568

8.3.4.4.2 SSI Raw Interrupt Status Register (SSIRIS) 569

8.3.4.4.3 SSI DMA Control Register (SSIDMACTL) 569

8.3.4.5 SSI Module Transmit/Receive Logic Control 570

8.3.4.6 SSI Modules Initialization and Con ﬁgurations 570

8.3.4.6.1 SSI-Module-Related GPIO Ports Initialization 570

8.3.4.6.2 SSI Module Initialization and Conﬁguration 571

8.3.4.6.3 SSI Module Clock Source and Bit Rate Initialization and

Conﬁguration 571

8.3.5 Build the On-Board LCD Interface Programming Project 572

8.3.5.1 SSI Module Interface for the LCD in EduBASE ARM



Trainer 572

8.3.5.2 The Serial Shift Register 74VHCT595 573

8.3.5.3 The LCD Module TC1602A and LCD Controller SPLC780 574

8.3.5.3.1 Interfacing Control Signals Between the MCU and the

SPLC780 576

8.3.5.3.2 Control and Interface Programming for SPLC780 578

8.3.5.3.3 LCD Programming Instruction Structure and Sequence 580

8.3.5.4 Build the Example LCD Interfacing Project 583

8.3.5.4.1 Create a Direct Register Access LCD Project DRALCD 584

8.3.5.4.2 Create the Header File DRALCD.h 584

8.3.5.4.3 Create the C Source File DRALCD.c 585

8.3.5.4.4 Set Up the Environment to Build and Run the Project 589

8.3.6 Build On-Board 7-Segment LED Interface Programming Project 589

8.3.6.1 Structure of 7-Segment LEDs 589

8.3.6.2 SSI Module Interface for the 7-Segment LED in the EduBASE ARM



Trainer 590

8.3.6.3 Build the Example LED Interfacing Project 592

8.3.6.3.1 Create a Direct Register Access LED Project DRALED 593

8.3.6.3.2 Create the C Source File DRALED.c 593

8.3.6.3.3 Set Up the Environment to Build and Run the Project 595

8.3.7 Build Digital-to-Analog Converter Programming Project 595

8.3.7.1 SSI Module Interface for the DAC-MCP4922 in the EduBASE ARM



Trainer 595

8.3.7.2 The Operations and Programming for MCP4922 DAC 596

8.3.7.3 The Analog-to-Digital Converter TLC-548 598

8.3.7.4 Build the Example DAC Interfacing Project 599

8.3.7.4.1 Create a Direct Register Access DAC Project DRADAC 600

xviii Contents

8.3.7.4.2 Create the Header File DRADAC.h 600

8.3.7.4.3 Create the C Source File DRADAC.c 600

8.3.7.4.4 Set Up the Environment to Build and Run the Project 603

8.3.8 SSI API Functions Provided by TivaWare

Peripheral Driver Library 604

8.3.8.1 The SSI Module Initialization and Conﬁguration Functions 604

8.3.8.2 The SSI Module Control and Status Functions 605

8.3.8.3 The SSI Module Data Processing Functions 606

8.3.8.4 The SSI Module Interrupt Source and Processing Functions 607

8.3.8.5 Build an Example Project to Interface Serial Peripherals Using the SSI

Module 608

8.3.8.5.1 Create a New Software Driver Model Project SDLCD 608

8.3.8.5.2 Create the Header File SDLCD.h 608

8.3.8.5.3 Create the C Source File SDLCD.c 608

8.4 Inter-Integrated Circuit (I2C) Interface 611

8.4.1 I2C Module Bus Conﬁguration and Operational Status 612

8.4.2 I2C Module Architecture and Functional Block Diagram 613

8.4.3 I2C Module Data Transfer Format and Frame 614

8.4.4 I2C Module Operational Sequence 614

8.4.4.1 I2C Module Works in the Master Transmit Mode 614

8.4.4.2 I2C Module Works in the Master Receive Mode 616

8.4.4.3 I2C Module Works in the Slave Transmit and Receive Modes 616

8.4.5 I2C Module Major Operational Components and Control Signals 618

8.4.6 I2C Module Running Speeds (Clock Rates) and Interrupts 620

8.4.6.1 I2C Module High-Speed Mode 621

8.4.6.2 I2C Module Interrupts Generation and Processing 621

8.4.6.2.1 I2C Master Interrupts 622

8.4.6.2.2 I2C Slave Interrupts 622

8.4.7 I2C Interface Control Signals and GPIO I2C Control Registers 622

8.4.8 I2C Module Control Registers and Their Functions 623

8.4.8.1 I2C Module Master Control Registers 623

8.4.8.1.1 I2C Master Slave Address Register (I2CMSA) 623

8.4.8.1.2 I2C Master Control/Status Register (I2CMCS) 624

8.4.8.1.3 I2C Master Data Register (I2CMDR) 624

8.4.8.1.4 I2C Master Timer Period Register (I2CMTPR) 624

8.4.8.1.5 I2C Master Conﬁguration Register (I2CMCR) 625

8.4.8.1.6 I2C Master Clock Low Timeout Count Register

(I2CMCLKOCNT) 625

8.4.8.1.7 I2C Master Bus Monitor Register (I2CMBMON) 626

8.4.8.1.8 I2C Master Interrupt Mask Register (I2CMIMR) 626

8.4.8.1.9 I2C Master Raw Interrupt Status Register (I2CMRIS) 626

8.4.8.1.10 I2C Master Masked Interrupt Status Register (I2CMMIS) 626

8.4.8.1.11 I2C Master Interrupt Clear Register (I2CMICR) 627

8.4.8.2 I2C Module Slave Control Registers 627

8.4.8.2.1 I2C Slave Own Address Register (I2CSOAR) 627

8.4.8.2.2 I2C Slave Control Status Register (I2CSCSR) 627

8.4.8.2.3 I2C Slave Data Register (I2CSDR) 628

8.4.8.2.4 I2C Slave Own Address 2 Register (I2CSOAR2) 628

Contents xix

8.4.8.2.5 I2C Slave ACK Control Register (I2CSACKCTL) 628

8.4.8.2.6 I2C Slave Interrupt Mask Register (I2CSIMR) 629

8.4.8.2.7 I2C Slave Raw Interrupt Status Register (I2CSRIS) 629

8.4.8.2.8 I2C Slave Masked Interrupt Status Register (I2CSMIS) 629

8.4.8.2.9 I2C Slave Interrupt Clear Register (I2CSICR) 629

8.4.9 I2C Module Initializations and Con ﬁgurations 630

8.4.9.1 Initializations and Conﬁgurations for the I2C-Related GPIO Pins 630

8.4.9.2 Initializations and Conﬁgurations for the I2C Module 630

8.4.10 Build an Example I2C Module Project 631

8.4.10.1 The BQ32000 Real Time Clock (RTC) 631

8.4.10.2 The Interface Between the BQ32000 and EduBASE ARM



Trainer 633

8.4.10.3 Create a DRA Model I2C Project DRAI2C 634

8.4.10.4 Create the Source File DRAI2C 634

8.4.10.5 Set Up the Environment to Build and Run the Project 638

8.4.11 I2C API Functions Provided by TivaWare

Peripheral Driver Library 639

8.4.11.1 Master Operations 639

8.4.11.2 I2C Module Status and Initialization API Functions 640

8.4.11.3 I2C Module Sending and Receiving Data API Functions 641

8.5 Universal Asynchronous Receivers/Transmitters (UARTs) 642

8.5.1 Asynchronous Serial Communication Protocols and Data Framing 642

8.5.2 Asynchronous Serial Interface Architecture and Functional Block

Diagram 643

8.5.3 UART Module Operations and Control Registers 645

8.5.3.1 Transmit/Receive Logic and Data Transmission and Receiving 645

8.5.3.2 UART Modem Handshake Support 645

8.5.3.3 UART FIFO Operations 647

8.5.3.4 UART Interrupts and DMA Control 648

8.5.3.5 UART Serial IR (SIR) Support 649

8.5.3.6 9-Bit UART Mode 649

8.5.3.7 UART Module Clock Control and Baud Rate Generation

Registers 650

8.5.3.8 UART Module Control/Status and FIFO Control Registers 651

8.5.3.8.1 UART Control Register (UARTCTL) 651

8.5.3.8.2 UART Line Control Register (UARTLCRH) 653

8.5.3.8.3 UART Receive Status/Error Clear Register

(UARTRSR/UARTECR) 653

8.5.3.8.4 UART Data Register (UARTDR) 654

8.5.3.8.5 UART Flag Register (UARTFR) 655

8.5.3.9 UART Module Interrupt and DMA Control Registers 655

8.5.3.9.1 UART Interrupt FIFO Level Select (UARTIFLS) Register 656

8.5.3.9.2 UART Raw Interrupt Status (UARTRIS) Register 656

8.5.3.9.3 UART Interrupt Mask (UARTIM) Register 656

8.5.3.9.4 UART Masked Interrupt Status (UARTMIS) Register 657

8.5.3.9.5 UART Interrupt Clear Register (UARTICR) 657

8.5.3.9.6 UART DMA Control (UARTDMACTL) Register 657

8.5.4 UART Module Control Signals and Related GPIO Pins 658

xx Contents

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