MSP430FG43X：超低功耗微控制器与能量测量应用

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"MSP430FG43X.pdf 是一份关于德州仪器(Texas Instruments)的MSP430系列超低功耗微控制器的文档，特别关注MSP430FE42x系列。该系列微控制器适用于单相电能测量应用，包括两线制和三线制电表，且具有反篡改功能。" MSP430系列微控制器是德州仪器推出的一种高效能、低功耗的16位微控制器，适合各种需要节能的便携式测量应用。其架构设计考虑了五个不同的低功耗模式，这使得它在延长电池寿命方面表现出色。MSP430FE42x系列特别之处在于它包含三个独立的16位sigma-delta模数转换器（ADC）和嵌入式信号处理器核心，用于单相能量的测量和计算，无论是在两线制还是三线制配置中。该微控制器的特性包括： 1. **16位RISC CPU**：高效的16位精简指令集计算机（RISC）处理器，结合16位寄存器，确保代码执行效率高。 2. **常量发生器**：有助于提高代码效率。 3. **数字控制振荡器(DCO)**：能够在不到6微秒的时间内从低功耗模式唤醒到活动模式，快速响应。 4. **16位定时器**：提供精确的时间测量和控制。 5. **128段LCD驱动能力**：支持显示功能。 6. **14个I/O引脚**：灵活的接口选项。 7. **低功耗特性**：包括低至300微安的1MHz活动模式功耗，1.1微安的待机模式功耗，以及0.1微安的关断模式（RAM保持）功耗。 8. **多种电源管理模式**：满足不同场景下的能耗需求。 9. **内置单通道直接存储器访问(DMA)**：提高数据传输效率。 10. **12位ADC**：带内部参考、采样保持和自动扫描功能，适用于精准的模拟输入转换。 11. **可配置运算放大器**：增强信号处理能力。 12. **双12位数模转换器(DAC)**：同步操作功能。 13. **两个16位定时器**：Timer_A和Timer_B，分别带有多个捕获/比较寄存器。 14. **片上比较器**：进行电压比较任务。 15. **串行通信接口(USART)**：通过软件选择异步UART或同步SPI通信模式。 16. **棕色out检测器**：防止电压过低导致的系统不稳定。 17. **电源电压监控器**：可编程的电压检测水平。 18. **引导加载程序**：方便固件更新。 19. **串行板载编程**：无需外部编程电压。 20. **程序保护**：通过安全熔丝实现可编程的代码保护。这些特性使MSP430FE42x系列微控制器成为单相电表和其他能源管理应用的理想选择，尤其是在对功耗敏感的系统中，如智能电网、家用电器和远程监测设备等。通过利用其强大的处理能力和低功耗特性，设计者能够创建出既高效又节能的解决方案。

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SLAS380A − APRIL 2004 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128

bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A and B can be erased individually, or as a group with segments 0−n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

Segment 0

w/ Interrupt Vectors

Segment 1

Segment 2

Segment n-1

Segment n†

Segment A

Segment B

Main

Memory

Information

Memory

32KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h

0F9FFh

48KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h

0F9FFh

60KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h

0F9FFh

08400h

083FFh

08200h

081FFh

08000h

010FFh

01080h

0107Fh

01000h

04400h

043FFh

04200h

041FFh

04000h

010FFh

01080h

0107Fh

01000h

01400h

013FFh

01200h

011FFh

01100h

010FFh

01080h

0107Fh

01000h

†

MSP430FG439 flash segment n = 256 bytes.

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SLAS380A − APRIL 2004 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature

Number SLAU056.

DMA controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using

the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system

power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to

or from a peripheral.

oscillator and system clock

The clock system in the MSP430FG43x family of devices is supported by the FLL+ module that includes support

for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency

crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and

low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction

with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.

The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module

provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.

D Main clock (MCLK), the system clock used by the CPU.

D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on

and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user

selectable level and supports both supply voltage supervision (the device is automatically reset) and supply

voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V

may not

have ramped to V

CC(min)

at that time. The user must insure the default FLL+ settings are not changed until V

reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when V

reaches V

CC(min)

digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

D All individual I/O bits are independently programmable.

D Any combination of input, output, and interrupt conditions is possible.

D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

D Read/write access to port-control registers is supported by all instructions.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both

timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and

clock for the LCD module.

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  

SLAS380A − APRIL 2004 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD

controller has dedicated data memory to hold segment drive information. Common and segment signals are

generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input

and output terminal is software-selectable and offers a flexible choice of connections for various applications.

The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

USART0

The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART)

peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4

pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number

Device Input

Module Input

Module

Module Output

Output Pin Number

Device Input

Signal

Module Input

Name

Module

Block

Module Output

Signal

62 - P1.5 TACLK TACLK

ACLK ACLK

Timer

SMCLK SMCLK

Timer NA

62 - P1.5 TACLK INCLK

67 - P1.0 TA0 CCI0A

67 - P1.0

66 - P1.1 TA0 CCI0B

CCR0

TA0

GND

CCR0 TA0

65 - P1.2 TA1 CCI1A

65 - P1.2

CAOUT (internal) CCI1B

CCR1

TA1

ADC12 (internal)

GND

CCR1 TA1

59 - P2.0 TA2 CCI2A

59 - P2.0

ACLK (internal) CCI2B

CCR2

TA2

GND

CCR2 TA2

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