Microsemi ProASIC3 FPGA低功耗闪存数据手册：A3P300特性与优势

需积分: 3 75 浏览量更新于2024-07-15 收藏 11.45MB PDF 举报

Microsemi公司的A3P300 FPGA datasheet是一份详尽的技术文档，涵盖了该公司在低功耗Flash技术方面的创新设计。这份200多页的文档主要介绍了ProASIC3系列FPGA，包括A3P250、A3P600、A3P1000和A3P3000等不同型号，适合对FPGA设计和低功耗技术感兴趣的工程师深入学习。该FPGA的核心特点和优势包括： 1. **低功耗设计**：通过采用1.2V至1.5V的低电压核心和I/O支持，显著降低动态和静态功耗。在Flash*Freeze模式下，能够实现瞬间进入和退出低功耗状态，同时保持极低的功耗消耗。 2. **单电压系统操作**：支持单电压系统运行，简化了电源管理，降低了复杂性。 3. **低阻抗开关**：确保信号传输效率，提高电路的信号完整性。 4. **高容量**：具有高达3,000,000个系统门，最多504kbit的True Dual-Port SRAM以及多达620个用户I/O接口，满足大型和高性能应用的需求。 5. **可编程Flash技术**：基于130-nm工艺的Flash-based CMOS工艺，提供了即时On-Level0支持，是一种单芯片解决方案，即使在关机状态下也能保持设计内容。 6. **高性能**：A3P300能够在1.5V系统中达到350MHz，而在1.2V系统中则为250MHz，同时支持多种外设速度，如3.3V的66MHz PCI。 7. **In-System Programming (ISP) 和安全**：内置128位AES加密功能，通过JTAG（符合IEEE 1532标准）进行ISP，提供高级安全性，FlashLock®技术能有效保护FPGA内部设计内容免受未经授权的访问。 8. **高性能路由层次结构**：文档还提及了高级的路由设计，允许高效的数据传输和信号处理。总结来说，这份A3P300 FPGA datasheet不仅提供了丰富的功能列表，还强调了Microsemi在低功耗、性能、容量和安全方面的技术实力。对于从事嵌入式系统、通信设备或数据中心应用的设计师来说，这是深入理解ProASIC3系列FPGA及其在实际项目中的应用的重要参考资料。

ProASIC3L DC and Switching Characteristics

2-2 Revision 13

Table 2-2 • Recommended Operating Conditions

Symbol Parameter Commercial Industrial Units

Ambient temperature 0 to +70 –40 to +85 °C

Junction Temperature 0 to + 85 –40 to +100 °C

VCC

1.2 V–1.5 V wide range core voltage

1.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP

Programming voltage Programming Mode

3.15 to 3.45 3.15 to 3.45 V

Operation

0 to 3.6 0 to 3.6 V

VCCPLL

Analog power supply (PLL) 1.2 V–1.5 V wide range

core voltage

1.14 to 1.575 1.14 to 1.575 V

VCCI and

VMV

1.2 V DC supply voltage

1.14 to 1.26 1.14 to 1.26 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V wide range DC supply voltage

2.7 to 3.6 2.7 to 3.6 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-14 on page 2-10. VCCI should be at the same voltage within a given I/O bank.

3. All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V.

4. The programming temperature range supported is T

ambient

= 0°C to 85°C.

5. VPUMP can be left floating during normal operation (not programming mode).

6. VCCPLL pins should be tied to VCC pins. See the "VCCPLA/B/C/D/E/F PLL Supply Voltage" section on page 3-1 for

further information.

7. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

8. For ProASIC

3L devices, VCCI



VCC.

9. 3.3 V wide range is compliant to the JESD8-A specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature

Product

Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature T

STG

(°C)

Maximum Operating

Junction Temperature T

(°C)

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3L Low Power Flash FPGAs

Revision 13 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits

VCCI

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/

Undershoot

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of

two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3L DC and Switching Characteristics

2-4 Revision 13

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup

behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-

2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low-Power Flash Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

剩余241页未读，继续阅读

MLJZJ

粉丝: 9
资源: 2

Microsemi ProASIC3 FPGA低功耗闪存数据手册：A3P300特性与优势

A3PE3000-FG484I

p300_codes.rar_P300_P300 Classification_P300检测分类_p300_codes_支持向量

EEG-P300Speller-Toolkit-master_P300信号的处理_p300eeg_P300_eegp300_EE

归档_P300_CNN_

CNN_P300-master.zip_P300_cnn/p300 .脑机接口_cnn接口_p300脑机_脑机接口

P300_speller

p300_fiberlaser_twoend_光纤激光器_激光器_

cnn_test_data_excel_process_p300预处理_CNN输入数据预处理_

p300.rar_P300特征提取_matlab p300脑电_matlab 脑电_小波变换 脑电_脑电 小波

最新资源

p300.rar_P300特征提取_matlab p300脑电_matlab 脑电_小波变换脑电_脑电小波