QorIQ P5020多核通信处理器家族参考手册概述

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本文档是Freescale Semiconductor公司发布的关于PowerPC 5020 QorIQ集成多核通信处理器家族参考手册，版本为Rev4，更新日期为2013年7月。P5020是一款高度集成的处理器，专为满足各种高性能应用需求设计，如路由器控制、DSP Farm控制、SAN RAID 6控制器以及打印机控制等。在1.1节中，介绍部分概述了P5020的特点，它旨在提供强大的多核处理能力，支持单个系统同时运行多个操作系统或通过简单的调度器在无操作系统的环境中运行。处理器提供了两种主要的运行选项：一是利用操作系统（OS）的优势，二是采用OS-less模式，通过定制的调度机制实现高效任务管理。 1.4节详细讨论了双核处理选择，无论是基于操作系统还是独立运行时，处理器都确保了良好的灵活性。在OS环境下，P5020能够充分利用硬件资源和操作系统内核的优势；而在OS-less模式下，它具备一个简单的任务调度器，可以有效地协调各个核心的工作。 1.4.2节重点介绍了多核处理中的DPAA（Dynamic Processing Acceleration Architecture），这是一种优化架构，允许处理器根据任务需求动态地分配计算资源，提高了系统的整体性能和响应速度。 1.6节列举了P5020在不同应用场景中的实际应用示例，如作为路由器控制处理器，提供高速路由决策和数据包处理；作为DSP Farm控制处理器，支持大规模并行数字信号处理任务；作为SAN RAID 6控制器，实现高级磁盘阵列管理和数据冗余保护；以及作为打印机控制处理器，确保打印机的高效和稳定运行。 1.7节深入探讨了P5020的子系统特性，包括e5500核心和缓存内存复杂结构。e5500核心具备先进的功能，如私有后端缓存（512-Kbyte）以及CoreNet平台缓存（CPC），以提高数据访问速度。此外，还包括CoreNet fabric（核心网络）和地址映射，以及内存复杂部分，如DDR内存控制器和预启动加载器（PreBoot Loader）及非易失性存储接口，确保了内存管理的高效和稳定。总结来说，PowerPC 5020 QorIQ集成多核通信处理器家族参考手册是一份全面的技术文档，涵盖了处理器的架构、运行模式、应用案例以及关键子系统的详细设计，对于理解和开发基于此处理器的系统具有重要参考价值。

Section number Title Page

10.2.3.2 PAACE Offset 0x08.................................................................................................................434

10.2.3.2.1 PAACE Domain Attributes ..............................................................................435

10.2.3.3 PAACE Offset 0x10.................................................................................................................436

10.2.3.4 PAACE Offset 0x18.................................................................................................................437

10.3 PAMU Memory Map/Register Definitions..................................................................................................................438

10.4 PAMU Memory Map....................................................................................................................................................438

10.4.1 Primary PAACT Base Address High register (PAMUx_PPBAH)..............................................................458

10.4.2 Primary PAACT Base Address Low register (PAMUx_PPBAL)...............................................................459

10.4.3 Primary PAACT Limit Address High register (PAMUx_PPLAH).............................................................459

10.4.4 Primary PAACT Limit Address Low register (PAMUx_PPLAL)..............................................................460

10.4.5 Secondary PAACT Base Address High register (PAMUx_SPBAH)..........................................................460

10.4.6 Secondary PAACT Base Address Low register (PAMUx_SPBAL)...........................................................461

10.4.7 Secondary PAACT Limit Address High register (PAMUx_SPLAH).........................................................461

10.4.8 Secondary PAACT Limit Address Low register (PAMUx_SPLAL)..........................................................461

10.4.9 OMT Base Address High register (PAMUx_OBAH)..................................................................................462

10.4.10 OMT Base Address Low register (PAMUx_OBAL)...................................................................................462

10.4.11 OMT Limit Address High register (PAMUx_OLAH).................................................................................463

10.4.12 OMT Limit Address Low register (PAMUx_OLAL)..................................................................................463

10.4.13 PAMU Address Capabilities Register 1 (PAMUx_PAC1)..........................................................................464

10.4.14 PAMU Address Capabilities Register 2 (PAMUx_PAC2)..........................................................................464

10.4.15 PAMU Operation Error Status register 1 (PAMUx_POES1)......................................................................465

10.4.16 PAMU Operation Error Status register 2 (PAMUx_POES2)......................................................................466

10.4.17 PAMU Operation Error Address High register (PAMUx_POEAH)...........................................................466

10.4.18 PAMU Operation Error Address Low register (PAMUx_POEAL)............................................................467

10.4.19 Access Violation Status register 1 (PAMUx_AVS1)..................................................................................468

10.4.20 Access Violation Status register 2 (PAMUx_AVS2)..................................................................................470

10.4.21 Access Violation Address High register (PAMUx_AVAH)........................................................................471

10.4.22 Access Violation Address Low register (PAMUx_AVAL).........................................................................471

10.4.23 ECC Error Control Register (PAMUx_EECTL).........................................................................................471

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Section number Title Page

10.4.24 ECC Error Interrupt Enable Register (PAMUx_EEINTEN).......................................................................472

10.4.25 ECC Error Detect Register (PAMUx_EEDET)...........................................................................................473

10.4.26 ECC Error Attributes Register (PAMUx_EEATTR)...................................................................................474

10.4.27 ECC Error Address High (PAMUx_EEAHI)..............................................................................................475

10.4.28 ECC Error Address Low (PAMUx_EEALO)..............................................................................................475

10.4.29 ECC Error Data High (PAMUx_EEDHI)....................................................................................................476

10.4.30 ECC Error Data Low (PAMUx_EEDLO)...................................................................................................476

10.4.31 Unauthorized device access detection register (PAMUx_UDAD)..............................................................477

10.4.32 PAMU Revision register 1 (PAMUx_PR1).................................................................................................477

10.4.33 PAMU Revision register 2 (PAMUx_PR2).................................................................................................478

10.4.34 PAMU Capabilities register 1 (PAMUx_PC1)............................................................................................478

10.4.35 PAMU Capabilities register 2 (PAMUx_PC2)............................................................................................479

10.4.36 PAMU Capabilities register 3 (PAMUx_PC3)............................................................................................480

10.4.37 PAMU Capabilities register 4 (PAMUx_PC4)............................................................................................482

10.4.38 PAMU Control register (PAMUx_PC)........................................................................................................483

10.4.39 PAMU Interrupt Control and Status register (PAMUx_PICS)....................................................................484

10.5 PAMU Functional Description.....................................................................................................................................485

10.5.1 System Set-Up for PAMU Operation..........................................................................................................485

10.5.2 Steps in Processing of DSA Operations by PAMU.....................................................................................486

10.5.3 Detailed Description of PAMU Actions......................................................................................................488

10.5.3.1 PAMU Gate Closed and PAMU Enable Check.......................................................................488

10.5.3.2 PPAACT Request Range Check..............................................................................................489

10.5.3.3 PPAACT Cache Lookup..........................................................................................................490

10.5.3.4 PAMU Fetch Request..............................................................................................................490

10.5.3.5 Primary PAACE Processing....................................................................................................490

10.5.3.6 SPAACE Access and Processing.............................................................................................492

10.5.3.6.1 SPAACT Request Range Check.......................................................................492

10.5.3.6.2 SPAACT Cache Lookup Request.....................................................................493

10.5.3.6.3 Secondary PAACE Processing.........................................................................493

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Section number Title Page

10.5.3.7 Address Translation Service....................................................................................................494

10.5.3.7.1 No Address Translation Mode..........................................................................494

10.5.3.7.2 Window Address Translation Mode.................................................................495

10.5.3.8 OMT Access and Service.........................................................................................................497

10.5.3.8.1 No Operation Translation.................................................................................497

10.5.3.8.2 Operation Type Translation..............................................................................498

10.5.3.8.3 OMT Cache Access..........................................................................................500

10.5.3.9 Access Violation......................................................................................................................501

10.6 PAMU Initialization/Application Information.............................................................................................................501

10.6.1 System Set-Up..............................................................................................................................................501

10.6.1.1 Setting Up PAMU....................................................................................................................501

10.6.1.2 Power-On Reset.......................................................................................................................502

10.6.2 System with Multiple PAMUs ....................................................................................................................502

10.6.2.1 PAACT Locations....................................................................................................................502

10.6.2.2 OMT Locations........................................................................................................................503

10.6.2.3 Location of PAACT and OMT Data Structures.......................................................................503

10.6.3 Peer-to-Peer I/O Operations.........................................................................................................................503

10.6.4 PAMU Cache Coherency.............................................................................................................................504

10.6.5 Quiescing I/O Devices.................................................................................................................................504

10.6.5.1 Quiescing I/O Devices for Table/Entry Updates.....................................................................505

10.6.5.2 Quiescing I/O Devices for Enabling PAMU and its Caches...................................................505

10.6.6 Locality of References.................................................................................................................................505

10.6.6.1 Spatial Locality........................................................................................................................505

10.6.6.2 Temporal Locality....................................................................................................................506

10.6.7 Recovering Address Space...........................................................................................................................506

10.6.7.1 Primary PAACT Address Window..........................................................................................506

10.6.7.2 Secondary PAACT Address Window......................................................................................506

10.6.7.3 Secondary Sub-Windows and PAACEs..................................................................................506

10.6.8 Data Structure Size and Alignment..............................................................................................................507

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Section number Title Page

10.7 PAMU Setup.................................................................................................................................................................507

10.7.1 PAMU Operation Encoding.........................................................................................................................507

10.7.1.1 Ingress Operation Encoding (IOE)..........................................................................................508

10.7.1.2 Egress Operation Encodings....................................................................................................508

10.7.1.3 IOE to EOE Translations.........................................................................................................510

10.7.1.3.1 PAMU Bypass Mode and No Operation Translation Mode.............................510

10.7.1.3.2 Immediate and Indexed Operation Translation Modes.....................................511

10.7.2 Domain Attributes........................................................................................................................................511

10.7.2.1 Constrained Domain Attribute.................................................................................................511

10.7.3 Implementation Attributes...........................................................................................................................512

10.7.4 Operation Mapping Table (OMT)................................................................................................................512

Chapter 11

DDR Memory Controller

11.1 DDR Introduction.........................................................................................................................................................513

11.2 DDR Features Summary...............................................................................................................................................514

11.2.1 DDR Modes of Operation............................................................................................................................515

11.3 DDR External Signal Descriptions...............................................................................................................................515

11.3.1 DDR Signals Overview................................................................................................................................515

11.3.2 DDR Detailed Signal Descriptions..............................................................................................................517

11.3.2.1 Memory Interface Signals........................................................................................................518

11.3.2.2 Clock Interface Signals............................................................................................................522

11.4 DDR Memory Controller Memory Map.......................................................................................................................523

11.4.1 Chip select n memory bounds (DDRx_CSn_BNDS)..................................................................................529

11.4.2 Chip select n configuration (DDRx_CSn_CONFIG)...................................................................................530

11.4.3 Chip select n configuration 2 (DDRx_CSn_CONFIG_2)............................................................................533

11.4.4 DDR SDRAM timing configuration 3 (DDRx_TIMING_CFG_3).............................................................534

11.4.5 DDR SDRAM timing configuration 0 (DDRx_TIMING_CFG_0).............................................................536

11.4.6 DDR SDRAM timing configuration 1 (DDRx_TIMING_CFG_1).............................................................539

11.4.7 DDR SDRAM timing configuration 2 (DDRx_TIMING_CFG_2).............................................................542

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Section number Title Page

11.4.8 DDR SDRAM control configuration (DDRx_DDR_SDRAM_CFG).........................................................546

11.4.9 DDR SDRAM control configuration 2 (DDRx_DDR_SDRAM_CFG_2)..................................................549

11.4.10 DDR SDRAM mode configuration (DDRx_DDR_SDRAM_MODE).......................................................552

11.4.11 DDR SDRAM mode configuration 2 (DDRx_DDR_SDRAM_MODE_2)................................................552

11.4.12 DDR SDRAM mode control (DDRx_DDR_SDRAM_MD_CNTL)..........................................................553

11.4.13 DDR SDRAM interval configuration (DDRx_DDR_SDRAM_INTERVAL)............................................556

11.4.14 DDR SDRAM data initialization (DDRx_DDR_DATA_INIT)..................................................................557

11.4.15 DDR SDRAM clock control (DDRx_DDR_SDRAM_CLK_CNTL).........................................................557

11.4.16 DDR training initialization address (DDRx_DDR_INIT_ADDR)..............................................................558

11.4.17 DDR training initialization extended address (DDRx_DDR_INIT_EXT_ADDRESS)..............................559

11.4.18 DDR SDRAM timing configuration 4 (DDRx_TIMING_CFG_4).............................................................560

11.4.19 DDR SDRAM timing configuration 5 (DDRx_TIMING_CFG_5).............................................................563

11.4.20 DDR ZQ calibration control (DDRx_DDR_ZQ_CNTL)............................................................................565

11.4.21 DDR write leveling control (DDRx_DDR_WRLVL_CNTL).....................................................................567

11.4.22 DDR Self Refresh Counter (DDRx_DDR_SR_CNTR)...............................................................................570

11.4.23 DDR Register Control Words 1 (DDRx_DDR_SDRAM_RCW_1)...........................................................571

11.4.24 DDR Register Control Words 2 (DDRx_DDR_SDRAM_RCW_2)...........................................................572

11.4.25 DDR write leveling control 2 (DDRx_DDR_WRLVL_CNTL_2)..............................................................573

11.4.26 DDR write leveling control 3 (DDRx_DDR_WRLVL_CNTL_3)..............................................................576

11.4.27 DDR SDRAM mode configuration 3 (DDRx_DDR_SDRAM_MODE_3)................................................578

11.4.28 DDR SDRAM mode configuration 4 (DDRx_DDR_SDRAM_MODE_4)................................................579

11.4.29 DDR SDRAM mode configuration 5 (DDRx_DDR_SDRAM_MODE_5)................................................580

11.4.30 DDR SDRAM mode configuration 6 (DDRx_DDR_SDRAM_MODE_6)................................................581

11.4.31 DDR SDRAM mode configuration 7 (DDRx_DDR_SDRAM_MODE_7)................................................581

11.4.32 DDR SDRAM mode configuration 8 (DDRx_DDR_SDRAM_MODE_8)................................................582

11.4.33 DDR Debug Status Register 1 (DDRx_DDRDSR_1).................................................................................583

11.4.34 DDR Debug Status Register 2 (DDRx_DDRDSR_2).................................................................................584

11.4.35 DDR Control Driver Register 1 (DDRx_DDRCDR_1)...............................................................................585

11.4.36 DDR Control Driver Register 2 (DDRx_DDRCDR_2)...............................................................................588

P5020 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. 4, 7/2013

20 Freescale Semiconductor, Inc.

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