AD652：高精度压频转换芯片技术详解

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"AD652是一款单片同步电压-频率转换器，由Analog Devices公司生产，具有高精度和抗干扰能力，适用于高精度数模转换应用。" AD652是一款高性能的压频转换芯片，其核心技术在于将输入电压信号转化为对应的频率输出。这种转换方式在许多领域，如数据采集、测量系统以及工业自动化中，都有广泛的应用。AD652的独特之处在于其卓越的线性误差性能，最大线性误差在1MHz全尺度频率时仅为0.005%，而在2MHz全尺度频率时也不超过0.02%，这确保了在宽频率范围内的转换精度。该芯片允许用户通过外部系统时钟设置全尺度频率，最高可达2MHz，这为设计者提供了灵活的系统配置可能性。AD652不需要关键的外部组件，简化了系统设计，同时内置了一个准确的5V参考电压源，其漂移极低，最大仅为25ppm/°C，确保了在不同温度条件下的稳定性能。 AD652支持双电源或单电源操作，可以适应各种供电环境，并且能够处理电压或电流输入，增强了其在不同应用中的适用性。此外，该芯片还符合MIL-STD-883标准，意味着它满足军用级的可靠性要求，能够在恶劣环境中稳定工作。 AD652是高精度测量和控制系统的理想选择，其高精度、低漂移和抗干扰能力使其在要求严苛的工业应用中表现出色。结合其灵活性和可靠性，AD652为设计工程师提供了构建高效能、高精确度数模转换系统的基础。无论是在实验室研究还是在工业生产线，AD652都能够满足对数据转换精度的高标准需求。

AD652

Rev. C | Page 6 of 28

THEORY OF OPERATION

A synchronous VFC is similar to other voltage-to-frequency

converters in that an integrator is used to perform a charge-

balance of the input signal with an internal reference current.

However, rather than using a one-shot as the primary timing

element, which requires a high quality and low drift capacitor, a

synchronous voltage-to-frequency converter (SVFC) uses an

external clock. This allows the designer to determine the system

stability and drift based upon the external clock selected. A

crystal oscillator may also be used if desired.

The SVFC architecture provides other system advantages

besides low drift. If the output frequency is measured by

counting pulses gated to a signal that is derived from the clock,

the clock stability is unimportant and the device simply

performs as a voltage-controlled frequency divider, producing a

high resolution A/D. If a large number of inputs must be

monitored simultaneously in a system, the controlled timing

relationship between the frequency output pulses and the user-

supplied clock greatly simplifies this signal acquisition. Also, if

the clock signal is provided by a VFC, the output frequency of

the SVFC is proportional to the product of the two input

voltages. Therefore, multiplication and A-to-D conversion on

two signals are performed simultaneously.

00798-002

TRIM

OP AMP OUT

OP AMP "–"

OP AMP "+"

10 VOLT INPUT

–V

COMP REF

COMP "+"

COMP "–"

ANALOG GND

DIGITAL GND

FREQ OUT

CLOCK INPUT

ONE

SHOT

AND

"D"

FLOP

QCK

1mA

20kΩ

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

REFERENCE

Figure 2. CERDIP Pin Configuration

The pinouts of the AD652 SVFC are shown in Figure 2 and

Figure 3. A block diagram of the device configured as an SVFC,

along with various system waveforms, is shown in Figure 4.

00798-003

OP AMP OU

OP AMP "–"

OP AMP "+"

5V INPUT

10V INPUT

COMP "+"

COMP "–"

ANALOG GND

DIGITAL GND

FREQ OUT

8V INPUT

OPTIONAL

10V INPUT

–V

CLOCK

INPUT

COMP REF

1mA

REFERENCE

NC = NO CONNECT

AND

"D"

FLOP

ONE

SHOT

10kΩ

16kΩ

4kΩ

AD652

SYNCHRONOUS

VOLTAGE-TO-FREQUENCY

CONVERTER

Figure 3. PLCC Pin Configuration

Figure 4 shows the typical up-and-down ramp integrator output

of a charge-balance VFC. After the integrator output has

crossed the comparator threshold and the output of the AND

gate has gone high, nothing happens until a negative edge of the

clock comes along to transfer the information to the output of

the D FLOP. At this point, the clock level is low, so the latch does

not change state. When the clock returns high, the latch output

goes high and drives the switch to reset the integrator; at the

same time, the latch drives the AND gate to a low output state.

On the very next negative edge of the clock, the low output state

of the AND gate is transferred to the output of the D FLOP.

When the clock returns high, the latch output goes low and

drives the switch back into the Integrate mode. At the same

time, the latch drives the AND gate to a mode where it

truthfully relays the information presented to it by the

comparator.

Because the reset pulses applied to the integrator are exactly one

clock period long, the only place where drift can occur is in a

variation of the symmetry of the switching speed with

temperature.

Since each reset pulse is identical, the AD652 SVFC produces a

very linear voltage-to-frequency transfer relation. Also, because

all reset pulses are gated by the clock, there are no problems

with dielectric absorption causing the duration of a reset pulse

to be influenced by the length of time since the last reset.

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