"RISC最新非特权模式架构文档：RISC-V指令集手册第一卷：非特权ISA"

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The RISC-V Instruction Set Manual Volume I: Unprivileged ISA is the latest document detailing the non-privileged mode architecture of the RISC-V instruction set. Edited by Andrew Waterman and Krste Asanovi´c, the document provides a comprehensive guide to the RISC-V architecture, with a focus on non-privileged operations. Contributors to the document include experts such as Arvind, Rimas Aviˇzienis, and Alex Bradbury, among others. The RISC-V ISA is designed to be simple, efficient, and extensible, making it ideal for a wide range of applications, from embedded systems to high-performance computing. The non-privileged mode architecture outlined in the manual provides a foundation for building secure and reliable systems, with features such as memory protection, virtual memory support, and interrupt handling. The manual covers a wide range of topics, including instruction formats, data types, and memory management. It also provides detailed information on the various RISC-V instructions, their encoding, and their operation. The manual serves as a valuable resource for developers, engineers, and researchers looking to implement the RISC-V architecture in their projects. Overall, the RISC-V Instruction Set Manual Volume I: Unprivileged ISA is a comprehensive and detailed guide to the RISC-V architecture, providing valuable insights into the design and operation of this innovative instruction set. With its focus on non-privileged operations, the manual is an essential resource for anyone working with RISC-V systems.

xiv Volume I: RISC-V Unprivileged ISA V20191214-draft

27.9 Machine-level Instruction-Set Extensions . . . . . . . . . . . . . . . . . . . . . . . . . 157

27.10Non-Standard Extension Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

27.11Subset Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

28 History and Acknowledgments 159

28.1 “Why Develop a new ISA?” Rationale from Berkeley Group . . . . . . . . . . . . . . 159

28.2 History from Revision 1.0 of ISA manual . . . . . . . . . . . . . . . . . . . . . . . . . 161

28.3 History from Revision 2.0 of ISA manual . . . . . . . . . . . . . . . . . . . . . . . . . 162

28.4 History from Revision 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

28.5 History from Revision 2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

28.6 History for Revision 2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

28.7 Funding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

A RVWMO Explanatory Material, Version 0.1 167

A.1 Why RVWMO? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

A.2 Litmus Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

A.3 Explaining the RVWMO Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

A.3.1 Preserved Program Order and Global Memory Order . . . . . . . . . . . . . . 170

A.3.2 Load Value Axiom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

A.3.3 Atomicity Axiom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

A.3.4 Progress Axiom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

A.3.5 Overlapping-Address Orderings (Rules 1–3) . . . . . . . . . . . . . . . . . . . 174

A.3.6 Fences (Rule 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

A.3.7 Explicit Synchronization (Rules 5–8) . . . . . . . . . . . . . . . . . . . . . . . 177

A.3.8 Syntactic Dependencies (Rules 9–11) . . . . . . . . . . . . . . . . . . . . . . . 179

A.3.9 Pipeline Dependencies (Rules 12–13) . . . . . . . . . . . . . . . . . . . . . . . 182

A.4 Beyond Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

A.4.1 Coherence and Cacheability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

A.4.2 I/O Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Chapter 1

Introduction

RISC-V (pronounced “risk-ﬁve”) is a new instruction-set architecture (ISA) that was originally

designed to support computer architecture research and education, but which we now hope will

also become a standard free and open architecture for industry implementations. Our goals in

deﬁning RISC-V include:



A completely open ISA that is freely available to academia and industry.



A real ISA suitable for direct native hardware implementation, not just simulation or binary

translation.



An ISA that avoids “over-architecting” for a particular microarchitecture style (e.g., mi-

crocoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom,

ASIC, FPGA), but which allows eﬃcient implementation in any of these.



An ISA separated into a small base integer ISA, usable by itself as a base for customized

accelerators or for educational purposes, and optional standard extensions, to support general-

purpose software development.



Support for the revised 2008 IEEE-754 ﬂoating-point standard [8].



An ISA supporting extensive ISA extensions and specialized variants.



Both 32-bit and 64-bit address space variants for applications, operating system kernels, and

hardware implementations.



An ISA with support for highly parallel multicore or manycore implementations, including

heterogeneous multiprocessors.



Optional variable-length instructions to both expand available instruction encoding space and

to support an optional dense instruction encoding for improved performance, static code size,

and energy eﬃciency.



A fully virtualizable ISA to ease hypervisor development.



An ISA that simpliﬁes experiments with new privileged architecture designs.

Commentary on our design decisions is formatted as in this paragraph. This non-normative text

can be skipped if the reader is only interested in the speciﬁcation itself.

The name RISC-V was chosen to represent the ﬁfth major RISC ISA design from UC Berkeley

(RISC-I [16], RISC-II [9], SOAR [23], and SPUR [12] were the ﬁrst four). We also pun on the

use of the Roman numeral “V” to signify “variations” and “vectors”, as support for a range of

2 Volume I: RISC-V Unprivileged ISA V20191214-draft

architecture research, including various data-parallel accelerators, is an explicit goal of the ISA

design.

The RISC-V ISA is deﬁned avoiding implementation details as much as possible (although com-

mentary is included on implementation-driven decisions) and should be read as the software-visible

interface to a wide variety of implementations rather than as the design of a particular hardware

artifact. The RISC-V manual is structured in two volumes. This volume covers the design of

the base unprivileged instructions, including optional unprivileged ISA extensions. Unprivileged

instructions are those that are generally usable in all privilege modes in all privileged architectures,

though behavior might vary depending on privilege mode and privilege architecture. The second

volume provides the design of the ﬁrst (“classic”) privileged architecture. The manuals use IEC

80000-13:2008 conventions, with a byte of 8 bits.

In the unprivileged ISA design, we tried to remove any dependence on particular microarchi-

tectural features, such as cache line size, or on privileged architecture details, such as page

translation. This is both for simplicity and to allow maximum ﬂexibility for alternative microar-

chitectures or alternative privileged architectures.

1.1 RISC-V Hardware Platform Terminology

A RISC-V hardware platform can contain one or more RISC-V-compatible processing cores to-

gether with other non-RISC-V-compatible cores, ﬁxed-function accelerators, various physical mem-

ory structures, I/O devices, and an interconnect structure to allow the components to communicate.

A component is termed a core if it contains an independent instruction fetch unit. A RISC-V-

compatible core might support multiple RISC-V-compatible hardware threads, or harts, through

multithreading.

A RISC-V core might have additional specialized instruction-set extensions or an added coprocessor.

We use the term coprocessor to refer to a unit that is attached to a RISC-V core and is mostly

sequenced by a RISC-V instruction stream, but which contains additional architectural state and

instruction-set extensions, and possibly some limited autonomy relative to the primary RISC-V

instruction stream.

We use the term accelerator to refer to either a non-programmable ﬁxed-function unit or a core that

can operate autonomously but is specialized for certain tasks. In RISC-V systems, we expect many

programmable accelerators will be RISC-V-based cores with specialized instruction-set extensions

and/or customized coprocessors. An important class of RISC-V accelerators are I/O accelerators,

which oﬄoad I/O processing tasks from the main application cores.

The system-level organization of a RISC-V hardware platform can range from a single-core micro-

controller to a many-thousand-node cluster of shared-memory manycore server nodes. Even small

systems-on-a-chip might be structured as a hierarchy of multicomputers and/or multiprocessors to

modularize development eﬀort or to provide secure isolation between subsystems.

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