IA-32架构系统编程指南

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"IA-32 Intel Architecture Software Developer's Manual Volume 3 System Programming Guide" IA-32架构是Intel公司设计的一种32位处理器架构，广泛应用于个人计算机领域，包括早期的 Pentium 系列到现代的 Core 和 Xeon 处理器。此手册《IA-32 Intel Architecture Software Developer’s Manual》分为三个卷：基本架构、指令集参考和系统编程指南，为开发者提供了全面的IA-32处理器的软件开发信息。第一卷“基本架构”涵盖了IA-32架构的基础知识，包括处理器组织结构、寄存器布局、内存模型、指令执行流程以及基本的编程模型。这一部分详细解释了CPU如何处理数据和指令，以及如何与操作系统和其他硬件组件交互。第二卷“指令集参考”列出了IA-32架构支持的所有指令，包括算术、逻辑、转移、浮点运算、多媒体扩展（如MMX、SSE、AVX系列）等，这些指令是编写汇编语言程序或理解编译器生成的机器码所必需的。第三卷“系统编程指南”是我们重点关注的部分，它详细介绍了如何在IA-32系统上进行操作系统级的编程，涉及的内容包括中断和异常处理、系统调用、内存管理、I/O操作、多处理器（SMP）环境下的编程、电源管理和性能监控等。这一卷对理解和实现操作系统内核、设备驱动程序以及其他低级系统软件至关重要。文档中的“2001年”可能指的是手册的版本年份，表明这份资料可能基于较早的IA-32处理器技术，但许多基本原理和概念在现代的x86处理器中仍然适用。 Intel在文档中明确指出，提供这些信息并不授予任何知识产权的许可，并且对于Intel产品的销售和使用，不承担任何明示或默示的保证，包括但不限于特定用途的适用性、商业性和侵犯任何专利、版权或其他知识产权的权利。此外，Intel产品不推荐用于医疗、救生或生命维持应用。 Intel可能会对规格和产品描述进行更改，这意味着开发者需要定期更新参考资料，以获取最新的硬件特性和支持。对于软件开发者来说，理解和掌握IA-32架构的系统编程知识是编写高效、可靠和兼容的软件的关键。

TABLE OF TABLES

xvi

PAGE

Table C-2. Exceptions Generated With x87 FPU Floating-Point Instructions . . . . . . . . . C-2

Table C-3. Exceptions Generated With the SSE Instructions . . . . . . . . . . . . . . . . . . . . . C-4

Table C-4. Exceptions Generated With the SSE2 Instructions . . . . . . . . . . . . . . . . . . . . C-6

Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS . . . . . E-8

Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD . . . . . . . . . . . . . . . . E-8

Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD. . . . . . . . . E-8

Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE . . . . . . . . . . . . . . . . . . . . . E-8

Table E-5. CMPPS.NLT, CMPSS.NLT, CMPSS.NLT, CMPSS.NLE . . . . . . . . . . . . . . . . E-8

Table E-6. COMISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9

Table E-7. UCOMISS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9

Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI . . . . . . . . . . . . . . . . . . . . E-9

Table E-9. MAXPS, MAXSS, MINPS, MINSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9

Table E-10. SQRTPS, SQRTSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9

Table E-11. #I - Invalid Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10

Table E-12. #Z - Divide-by-Zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11

Table E-13. #D - Denormal Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12

Table E-14. #O - Numeric Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12

Table E-15. #U - Numeric Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13

Table E-16. #P - Inexact Result (Precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13

1-1

CHAPTER 1

ABOUT THIS MANUAL

The IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order

Number 245470) is part of a three-volume set that describes the architecture and programming

environment of all IA-32 Intel

Architecture processors. The other two volumes in this set are:

• The IA-32 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set

Reference (Order Number 245471).

• The IA-32 Intel Architecture Software Developer’s Manual, Volume 3: System

Programming Guide (Order Number 245472).

The IA-32 Intel Architecture Software Developer’s Manual, Volume 1, describes the basic archi-

tecture and programming environment of an IA-32 processor; the IA-32 Intel Architecture Soft-

ware Developer’s Manual, Volume 2, describes the instruction set of the processor and the

opcode structure. These two volumes are aimed at application programmers who are writing

programs to run under existing operating systems or executives. The IA-32 Intel Architecture

Software Developer’s Manual, Volume 3 describes the operating-system support environment of

an IA-32 processor, including memory management, protection, task management, interrupt and

exception handling, and system management mode. It also provides IA-32 processor compati-

bility information. This volume is aimed at operating-system and BIOS designers and program-

mers.

1.1. IA-32 PROCESSORS COVERED IN THIS MANUAL

This manual includes information pertaining primarily to the most recent IA-32 processors,

which include the Pentium

processors, the P6 family processors, the Pentium

4 processors,

and the Intel

Xeon™ processors. The P6 family processors are those IA-32 processors based

on the P6 family micro-architecture. This family includes the Pentium

Pro, Pentium

II, and

Pentium

III processors. The Pentium 4 and Intel Xeon processors are the first of a family of IA-

32 processors based on the new Intel

NetBurst™ micro-architecture.

1.2. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE

SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC

ARCHITECTURE

The contents of this manual are as follows:

Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Intel

Architecture Software Developer’s Manual. It also describes the notational conventions in these

manuals and lists related Intel manuals and documentation of interest to programmers and hard-

ware designers.

1-2

ABOUT THIS MANUAL

Chapter 2 — Introduction to the IA-32 Architecture. Introduces the IA-32 architecture and

the families of Intel processors that are based on this architecture. It also gives an overview of

the common features found in these processors and brief history of the IA-32 architecture.

Chapter 3 — Basic Execution Environment. Introduces the models of memory organization

and describes the register set used by applications.

Chapter 4 — Data Types. Describes the data types and addressing modes recognized by the

processor; provides an overview of real numbers and floating-point formats and of floating-

point exceptions.

Chapter 5 — Instruction Set Summary. Lists the all the IA-32 architecture instructions,

divided into technology groups (general-purpose, x87 FPU, MMX™ technology, Streaming

SIMD Extensions (SSE), Streaming SIMD Extensions 2 (SSE2), and system instructions).

Within these groups, the instructions are presented in functionally related groups.

Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack

and the mechanisms provided for making procedure calls and for servicing interrupts and

exceptions.

Chapter 7 — Programming With the General-Purpose Instructions. Describes the basic

load and store, program control, arithmetic, and string instructions that operate on basic data

types and on the general-purpose and segment registers; describes the system instructions that

are executed in protected mode.

Chapter 8 — Programming With the x87 Floating Point Unit. Describes the x87 floating-

point unit (FPU), including the floating-point registers and data types; gives an overview of the

floating-point instruction set; and describes the processor's floating-point exception conditions.

Chapter 9 — Programming with Intel MMX Technology. Describes the Intel MMX tech-

nology, including MMX registers and data types, and gives an overview of the MMX instruction

set.

Chapter 10 — Programming with Streaming SIMD Extensions (SSE). Describes the SSE

extensions, including the XMM registers, the MXCSR register, and the packed single-precision

floating-point data types; gives an overview of the SSE instruction set; and gives guidelines for

writing code that accesses the SSE extensions.

Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2). Describes the

SSE2 extensions, including XMM registers and the packed double-precision floating-point data

types; gives an overview of the SSE2 instruction set; and gives guidelines for writing code that

accesses the SSE2 extensions. This chapter also describes the SIMD floating-point exceptions

that can be generated with SSE and SSE2 instructions, and it gives general guidelines for incor-

porating support for the SSE and SSE2 extensions into operating system and applications code.

Chapter 12 — Input/Output. Describes the processor’s I/O mechanism, including I/O port

addressing, the I/O instructions, and the I/O protection mechanism.

Chapter 13 — Processor Identification and Feature Determination. Describes how to deter-

mine the CPU type and the features that are available in the processor.

Appendix A — EFLAGS Cross-Reference. Summarizes how the IA-32 instructions affect the

flags in the EFLAGS register.

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