![](https://csdnimg.cn/release/download_crawler_static/85169273/bg13.jpg)
JEDEC Standard No. 84-B51
-xv-
Table 191 — Secure Removal Type .......................................................................................................................... 230
Table 192 — Command Queue Mode Enable ........................................................................................................... 230
Table 193 — SECURE_WP_MODE_ENABLE ....................................................................................................... 231
Table 194 — SECURE _WP_MODE_CONFIG ...................................................................................................... 232
Table 195 — Error correction codes.......................................................................................................................... 233
Table 196 — DSR register content ............................................................................................................................ 242
Table 197 — General operating conditions ............................................................................................................... 244
Table 198 — e•MMC power supply voltage ............................................................................................................. 246
Table 199 — e•MMC voltage combinations ............................................................................................................. 246
Table 200 — Capacitance and Resistors ................................................................................................................... 247
Table 201 — AC Overshoot/Undershoot Specification ............................................................................................ 249
Table 202 — Open-drain bus signal level ................................................................................................................. 250
Table 203 — Push-pull signal level—high-voltage e•MMC ..................................................................................... 250
Table 204 — Push-pull signal level—1.70 V -1.95 V V
CCQ
voltage Range .............................................................. 250
Table 205 — Push-pull signal level—1.1 V-1.3 V V
CCQ
range e•MMC ................................................................... 250
Table 206 — I/O driver strength types ...................................................................................................................... 251
Table 207 — Driver Type-0 AC Characteristics ...................................................................................................... 252
Table 208 — High-speed Device interface timing .................................................................................................... 253
Table 209 — Backward-compatible Device interface timing.................................................................................... 254
Table 210 — High-speed dual rate interface timing .................................................................................................. 256
Table 211 — HS200 Clock signal timing .................................................................................................................. 257
Table 212 — HS200 Device input timing ................................................................................................................. 258
Table 213 — Output timing ....................................................................................................................................... 259
Table 214 — Temperature Conditions ...................................................................................................................... 260
Table 215 — HS400 Device input timing ................................................................................................................. 261
Table 216 — HS400 Device Output timing .............................................................................................................. 262
Table 217 — HS400 Capacitance and Resistors ....................................................................................................... 263
Table 218 — HS400 CMD Response timing ............................................................................................................ 264
Table 219 — e•MMC host requirements for Device classes ..................................................................................... 266
Table 220 — New Features List for device type ....................................................................................................... 267
Table A.221 — Macro commands ............................................................................................................................. 270
Table A.222 — Forward-compatible host interface timing ....................................................................................... 280
Table A.223 — Bus testing for eight data lines ......................................................................................................... 283
Table A.224 — Bus testing for four data lines .......................................................................................................... 283
Table A.225 — Bus testing for one data line............................................................................................................. 283
Table A.226 — XNOR values ................................................................................................................................... 284
Table A.227 — Package Case Temp (Tc) per current consumption ......................................................................... 290
Table B.228 — Handling of Error Conditions in CQE.............................................................................................. 301
Table B.229 — Task Descriptor Structure; Lower 64 bits (Data Transfer tasks) ...................................................... 302
Table B.230 — Task Descriptor Structure; Upper 64 bits ......................................................................................... 302
Table B.231 — Task Descriptor Fields ..................................................................................................................... 303
Table B.232 — Transfer Descriptor Structure (32-bit addressing) ............................................................................ 304
Table B.233 — Transfer Descriptor Structure (64-bit addressing) ............................................................................ 304
Table B.234 — Transfer Descriptor Fields ............................................................................................................... 304
Table B.235 — Task Descriptor Structure: Lower 64 bits (for DCMD tasks) .......................................................... 305
Table B.236 — Task Descriptor Fields (for DCMD tasks) ....................................................................................... 305
Table B.237 — CQE Register Map ........................................................................................................................... 307