可重复设计方法学在ASIC系统级芯片设计中的应用

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"IC 可重复设计方法学是ASIC设计中的关键思想，旨在提升设计效率和质量。通过采用标准化的设计模块和接口，实现设计元素的复用，从而降低设计复杂度，缩短产品上市时间，并提高设计的一致性和可靠性。本文档由Michael Keating和Pierre Bricaud合作撰写，分别来自Synopsys, Inc.和Mentor Graphics Corporation，两家在半导体设计领域具有影响力的公司。" 在ASIC设计中，"可重复设计"（Reuse Methodology）是一种系统级芯片（System-on-a-Chip, SoC）设计的重要策略。它强调设计不仅仅是为了单一用途，而是为了能够在不同的设计项目中重复使用。文档《REUSE METHODOLOGY MANUAL FOR SYSTEM-ON-A-CHIP DESIGNS》探讨了这一方法学的核心原则和实施技术。 1.1.1 设计目标和假设：文档的目标在于提供一套方法学，使得设计团队能够高效地创建和复用设计组件。其基础假设是，通过标准化和模块化，可以克服设计复杂性，促进设计流程的协同工作。 1.1.2 定义：文档可能定义了关键术语，如“虚拟插座接口联盟”（Virtual Socket Interface Alliance, VSIA），这是一个推动IC设计接口标准的行业组织，致力于提升设计的互操作性和可重用性。 1.1.3 基本问题：文档会深入探讨在设计复用过程中遇到的基础挑战，如设计的兼容性、接口的标准化以及不同设计之间的集成难题。 1.2.1 设计为使用：设计不仅需要满足功能需求，还需要考虑如何方便地被其他设计所使用，这意味着需要关注设计的可维护性和扩展性。 1.2.2 设计为复用：这是设计的关键目标，旨在创建可独立于具体应用而复用的设计单元，以减少重复劳动，提高设计生产力。 1.2.3 核心问题：文档可能会详细阐述在实现设计复用时所面临的挑战，如知识产权（IP）保护、设计验证的复杂性、以及不同工艺节点下的兼容性问题。 2.1 系统级芯片设计流程：文中将介绍一个典型的SoC设计流程，涵盖从概念到实现的各个阶段，包括需求分析、架构设计、模块划分、逻辑综合、布局布线、验证等步骤，每个步骤都可能涉及到可重复设计的方法和工具。 "IC 可重复设计方法学"是SoC设计中的一个重要概念，涉及多个层次的工程实践，包括设计规范、模块化、接口设计、IP管理、验证策略等多个方面。通过理解并应用这些方法，设计师能够更有效地构建复杂且高效的SoC解决方案。

xvi Reuse Methodology Manual

2 Reuse Methodology Manual

1.1 Goals of This Document

Development methodology necessarily differs between system designers and ASSP

designers, as well as between DSP developers and chipset developers. However, there

is a common set of problems facing everyone who is designing SoC-scale ASICs:

• Time-to-market pressures demand rapid development.

• Quality of results, in performance, area, and power, are key to market success.

• Increasing chip complexity makes veriﬁcation more difﬁcult.

• The development team has different levels and areas of expertise, and is often scat-

tered throughout the world.

• Design team members may have worked on similar designs in the past, but cannot

reuse these designs because the design ﬂow, tools, and guidelines have changed.

• SoC designs include embedded processor cores, and thus a signiﬁcant software

component, which leads to additional methodology, process, and organizational

challenges.

In response to these problems, many design teams are turning to a block-based design

approach that emphasizes design reuse. Reusing macros (sometimes called “cores”)

that have already been designed and veriﬁed helps to address all of the above prob-

lems. However, ASIC design for reuse is a new paradigm in hardware design. Ironi-

cally, many researchers in software design reuse point to hardware design as the

prime model for design reuse, in terms of reusing the same chips in different combi-

nations to create many different board designs. However, most ASIC design teams do

not code their RTL or design their testbenches with reuse in mind and, as a result,

most designers ﬁnd it faster to develop modules from scratch than to reverse engineer

someone else’s design.

Some innovative design teams are trying to change this pattern and are developing

effective design reuse strategies. This document focuses on describing these tech-

niques. In particular, it describes:

• How reusable macros ﬁt into a System-on-a-Chip development methodology

• How to design reusable soft macros

• How to design reusable hard macros

• How to integrate soft and hard macros into a System-on-a-Chip design

• How to verify timing and functionality in large System-on-a-Chip designs

In doing so, this document addresses the concerns of two distinct audiences: the cre-

ators of reusable designs (macro authors) and chip designers who use these reusable

blocks (macro integrators). For macro authors, the main sections of interest will be

those on how to design reusable hard and soft macros, and the other sections will be

Introduction 3

primarily for reference. For integrators, the sections on designing hard and soft mac-

ros are intended primarily as a description of what to look for in reusable designs.

System-on-a-Chip designs are made possible by deep submicron technology. This

technology presents a whole set of design challenges. Interconnect delays, clock and

power distribution, and place and route of millions of gates are real challenges to

physical design in the deep submicron technologies. These physical design problems

can have a signiﬁcant impact on the functional design of systems on a chip and on the

design process itself. Interconnect issues, ﬂoorplanning, and timing design must be

addressed early in the design process, at the same time as the development of the

functional requirements. This document addresses issues and problems related to pro-

viding logically robust designs that can be fabricated on deep submicron technologies

and that, when fabricated, will meet the requirements for clock speed, power, and

area.

System-on-a-Chip designs have a signiﬁcant software component in addition to the

hardware itself. However, this manual focuses primarily on the creation and reuse of

reusable hardware macros. This focus on hardware reuse should not be interpreted as

an attempt to minimize the importance in the software aspects of system design. Soft-

ware plays an essential role in the design, integration, and test of SoC systems, as well

as in the ﬁnal product itself.

1.1.1 Assumptions

This document assumes that the reader is familiar with standard high-level design

methodology, including:

• HDL design and synthesis

• Design for test, including full scan techniques

• Floorplanning and place and route

1.1.2 Deﬁnitions

In this document, we will use the following terms interchangeably:

• Macro

• Core

• Block

All of these terms refer to a design unit that can reasonably be viewed as a stand-alone

sub-component of a complete System-on-Chip design. Examples include a PCI inter-

face macro, a microprocessor core, or an on-chip memory.

4 Reuse Methodology Manual

Other terms used throughout this document include:

• Subblock – A subblock is a sub-component of a macro, core, or block. It is too

small or speciﬁc to be a stand-alone design component.

• Hard macro – A hard macro (or core or block) is one that is delivered to the inte-

grator as a GDSII ﬁle. It is fully designed, placed, and routed by the supplier.

• Soft macro – A soft macro (or core or block) is one that is delivered to the inte-

grator as synthesizable RTL code.

1.1.3 Virtual Socket Interface Alliance

The Virtual Socket Interface Alliance (VSIA) is an industry group working to facili-

tate the adoption of design reuse by setting standards for tool interfaces and design

practices. VSIA has done an excellent job in raising industry awareness of the impor-

tance of reuse and of identifying key technical issues that must be addressed to sup-

port widespread and effective design reuse.

The working groups of the VSIA have developed a number of proposals for standards

that are currently in review. To the extent that detailed proposals have been made, this

document attempts to be compliant with them.

Some exceptions to this position are:

• Virtual component: VSIA has adopted the name “virtual component” to specify

reusable macros. We have used the shorter term “macro” in most cases.

• Firm macro: VSIA has deﬁned an intermediate form between hard and soft mac-

ros, with a fairly wide range of scope. Firm macros can be delivered in RTL or

netlist form, with or without detailed placement, but with some form of physical

design information to supplement the RTL itself. We do not address ﬁrm macros

speciﬁcally in this document; we feel that it is more useful to focus on hard and

soft macros. As technology evolves for more tightly coupling synthesis and physi-

cal design, we anticipate that the category of ﬁrm macros will be merged with that

of soft macros.

1.2 Design for Reuse: The Challenge

An effective block-based design methodology requires an extensive library of reus-

able blocks, or macros. The developers of these macros must, in turn, employ a design

methodology that consistently produces reusable macros. This design reuse method-

ology is based on the following principles:

• Creation of every stage of design, from speciﬁcation to silicon, with the under-

standing that it will be modiﬁed and reused in other projects by other design teams

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