FT2232H：双高速USB多功能UART/FIFO芯片

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"FT2232H是Future Technology Devices International Limited公司的一款双通道高速USB到多功能UART/FIFO集成电路，具备多种配置以适应不同行业的串行或并行接口需求。这款芯片是FTDI的第五代USB设备，支持USB 2.0高速（480Mbps）和全速（12Mbps）兼容性。它具有集成的USB协议处理功能，无需特定的USB固件编程。FT2232H还配备了双多协议同步串行引擎（MPSSE），简化了同步串行协议设计，如USB到JTAG、I2C、SPI或电平转换。此外，该芯片提供两个独立的UART、FIFO或MPSSE端口，每个端口都有独立的波特率发生器，支持RS232/RS422/RS485 UART传输速率高达12Mbps（RS232速率受限于外部线路电容）。" FT2232H芯片是一款高度集成的USB接口解决方案，专为满足多样化应用需求而设计。它的主要特点包括： 1. **单芯片USB到双串行/并行端口**：FT2232H可以配置为各种行业标准的串行或并行接口，提供灵活的接口选择。 2. **内置USB协议处理**：芯片内部处理整个USB协议，这意味着开发人员无需编写特定的USB固件，简化了开发流程。 3. **USB 2.0高速兼容性**：支持480Mbps的高速模式和12Mbps的全速模式，确保高速数据传输。 4. **双多协议同步串行引擎（MPSSE）**：通过MPSSE，开发者可以轻松实现USB到JTAG、I2C、SPI等同步串行协议的转换，降低了同步串行协议设计的复杂性。 5. **独立的双端口**：FT2232H提供两个独立的UART、FIFO或MPSSE端口，允许同时进行两个不同的通信任务，提高系统效率。 6. **独立波特率发生器**：每个端口都可以设置不同的波特率，满足不同通信速度的需求。 7. **RS232/RS422/RS485支持**：作为UART，FT2232H支持这些工业标准的串行通信协议，传输速率最高可达12Mbps，但RS232的实际速率可能因外部电路条件而受限。这款芯片广泛应用于需要高速USB连接以及灵活串行接口的系统，如嵌入式系统、测试与测量设备、工业自动化和控制设备等。由于其强大的功能和易于使用的特性，FT2232H成为了许多开发者和工程师首选的USB到串行转换器。

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Version 2.21

Clearance No.: FTDI#77

3.4 Configured Pins

The following sections describe the function of the configurable pins referred to in the table given in

Section 3.2 which is determined by how the FT2232H is configured.

3.4.1 FT2232H pins used in an RS232 interface

The FT2232H channel A or channel B can be configured as an RS232 interface. When configured in this

mode, the pins used and the descriptions of the signals are shown in Table 3.4.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

RS232 Configuration Description

TXD

OUTPUT

TXD = transmitter output

RXD

INPUT

RXD = receiver input

RTS#

OUTPUT

RTS# = Ready To send handshake output

CTS#

INPUT

CTS# = Clear To Send handshake input

DTR#

OUTPUT

DTR# = Data Transmit Ready modem signaling line

DSR#

INPUT

DSR# = Data Set Ready modem signaling line

DCD#

INPUT

DCD# = Data Carrier Detect modem signaling line

RI#

INPUT

RI# = Ring Indicator Control Input. When the Remote Wake

up option is enabled in the EEPROM, taking RI# low can be

used to resume the PC USB Host controller from suspend.

(Also see note 1, 2, 3 in section 4.12)

TXDEN

OUTPUT

TXDEN = (TTL level). For use with RS485 level converters.

RXLED#

OUTPUT

RXLED = Receive signaling output when data is transferred

from FT2232H to USB Host. Pulses low when receiving data

(RXD) via USB. This should be connected to an LED.

TXLED#

OUTPUT

TXLED = Transmit signaling output when data is transferred

from USB Host to FT2232H. Pulses low when transmitting

data (TXD) via USB. This should be connected to an LED.

Table 3.4 Channel A and Channel B RS232 Configured Pin Descriptions

配置引脚

以下各节描述了在给定的表所述的配置引脚功能

3.2节是由FT2232H是如何配置的确定

在一个RS232接口用于FT2232H管脚

该FT2232H通道A或通道B可以配置为RS232接口。当以这种方式构造,管脚和使用的信号的描述示于表3.4.

TXD =发送器输出

RXD =接收器输入

RTS＃=准备发送握手输出

CTS＃=清除发送输入握手

DTR＃=数据发送就绪调制解调器的信号线

DSR＃=数据集就绪调制解调器的信号线

DCD＃=数据载波检测调制解调器的信号线

RI＃=环形指示器控制输入.当远程

醒来选项在EEPROM中启用,同时RI＃低,可用于恢复从暂停

电脑的USB主机控制器

TXDEN =（TTL电平）.对于RS485电平转换器使用.

RXLED =接收信号输出.低脉冲通过USB接口接收数据（

RXD）时.这应该被连接到LED.

TXLED =发送信号输

出.低脉冲通过USB传

输数据（TXD）时.这

应该被连接到LED

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Version 2.21

Clearance No.: FTDI#77

3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface

The FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.5. To

enter this mode the external EEPROM must be set to make port A 245 mode. A software command (Set

Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel

synchronous FIFO mode. In this mode the „B‟ channel is not available as all resources have been switched

onto channel A. In this mode, data is written or read on the rising edge of the CLKOUT.

Channel A

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

ADBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input unless

OE# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low, there is data

available in the FIFO which can be read by driving RD# low. When in

synchronous mode, data is transferred on every clock that RXF# and

RD# are both low. Note that the OE# pin must be driven low at least

1 clock period before asserting RD# low.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data can be

written into the FIFO by driving WR# low. When in synchronous

mode, data is transferred on every clock that TXE# and WR# are both

low.

RD#

INPUT

Enables the current FIFO data byte to be driven onto D0...D7 when

RD# goes low. The next FIFO data byte (if available) is fetched from

the receive FIFO buffer each CLKOUT cycle until RD# goes high.

WR#

INPUT

Enables the data byte on the D0...D7 pins to be written into the

transmit FIFO buffer when WR# is low. The next FIFO data byte is

written to the transmit FIFO buffer each CLKOUT cycle until WR# goes

high.

CLKOUT

OUTPUT

60 MHz Clock driven from the chip. All signals should be synchronized

to this clock.

OE#

INPUT

Output enable when low to drive data onto D0-7. This should be

driven low at least 1 clock period before driving RD# low to allow for

data buffer turn-around.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two functions on a

single pin. If USB is in suspend mode (PWREN# = 1) and remote

wakeup is enabled in the EEPROM , strobing this pin low will cause the

device to request a resume on the USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low any

data in the device TX buffer will be sent out over USB on the next

Bulk-IN request from the drivers regardless of the pending packet

size. This can be used to optimize USB transfer speed for some

applications. Tie this pin to VCCIO if not used. (Also see note 1, 2, 3

in section 4.12)

Table 3.5 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.4

在FT245风格同步FIFO接口使用FT2232H引脚

该FT2232H唯一通道A可以配置为一个FT245款式同步FIFO接口.何时

配置在该模式中,所使用的针和信号的描述示于表3.5.至

进入此模式下,外部EEPROM必须被设置为使A口245模式.软件命令（设置

位模式选项）,然后由应用程序发送到FTDI驱动程序告诉芯片进入单通道同步FIFO模式.在这种模式下,'B'信道不可用，

因为所有的资源都被切换到信道A.在这种模式下,数据被写入或读

取在CLKOUT的上升沿。

D7到D0双向FIFO数据.该总线通常是输入,除非OE＃为低

当高，不从FIFO中读取数据.当低,有数据,其中可以通过驱动RD＃低

可读取FIFO可用.当在同步模式中,数据传输在每个时钟是RXF＃和

RD＃都很低.请注意,OE＃引脚必须拉低至少1个时钟周期断言RD＃低

前

当高,不写数据到FIFO.当低,可将数据写入到FIFO通过驱动WR＃低.

当在同步模式下,

数据传输在每个时钟的TXE＃和WR＃都很低

使当前FIFO的数据字节被驱动到D0 ... D7

当RD＃变低.下一个FIFO的数据字节（如果有的话）是从接收FIFO缓冲器每个CLKOUT的循环,直到取

WR＃goes高

使得在D0的数据字节... D7 pins被写入到

发送FIFO缓冲区时,WR＃低.下一个FIFO的数据字节

被写入发送FIFO缓冲器每个CLKOUT的周期,直到WR＃goes高

从芯片60 MHz时钟驱动.所有信号应与此时钟同步

输出使能低时,驱动数据到D0-7.这应该是驱动的驱动RD＃低到允许数

据缓冲掉头前低至少1个时钟周期.

发送即时/唤醒信号结合在一个引脚两种功能.如果USB是在（

PWREN＃= 1）和远程唤醒是在EEPROM中启用,选通该管脚低会造成

设备要求就USB总线简历挂起模式

通常情况下,这可以用来唤醒主机PC

在正常操作（PWREN＃= 0）,如果该引脚为低电平在设备TX缓冲区中

的所有数据将被发送出去,通过USB从驱动程序的下一个批量IN请求,无

论以待数据包大小.这可以被用来优化USB传输速度的一些应用.配合这

个引脚VCCIO如果不使用

表3.5通道A FT245型同步FIFO配置的引脚说明

对于这种模式的功能说明,请参阅第4.4 FT245同步FIFO接口模式说明

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Version 2.21

Clearance No.: FTDI#77

3.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface

The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.6. To

enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,

data is written or read on the falling edge of the RD# or WR# signals.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input

unless RD# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low,

there is data available in the FIFO which can be read by

driving RD# low. When RD# goes high again RXF# will

always go high and only become low again if there is

another byte to read. During reset this signal pin is tri-

state, but pulled up to VCCIO via an internal 200kΩ

resistor.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data

can be written into the FIFO by strobing WR# high, then

low. During reset this signal pin is tri-state, but pulled up to

VCCIO via an internal 200kΩ resistor.

RD#

INPUT

Enables the current FIFO data byte to be driven onto

D0...D7 when RD# goes low. Fetches the next FIFO data

byte (if available) from the receive FIFO buffer when RD#

goes high.

WR#

INPUT

Writes the data byte on the D0...D7 pins into the transmit

FIFO buffer when WR# goes from high to low.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two

functions on a single pin. If USB is in suspend mode

(PWREN# = 1) and remote wakeup is enabled in the

EEPROM , strobing this pin low will cause the device to

request a resume on the USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is

strobed low any data in the device TX buffer will be sent out

over USB on the next Bulk-IN request from the drivers

regardless of the pending packet size. This can be used to

optimize USB transfer speed for some applications. Tie this

pin to VCCIO if not used. (Also see note 1, 2, 3 in section

4.12)

Table 3.6 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions

在FT245型异步FIFO接口使用FT2232H引脚

该FT2232H通道A或通道B可以被配置为一个FT245异步FIFO接口.当以这种方式构造,销和使用的信号的描述示于

表3.6.要进入此模式的外部EEPROM必须被设置为使端口A或B或两者兼而有之245模式.在这种模式下,数据被写入或

读取的RD＃或WR＃信号的下降沿

通道A引脚号

通道B引脚号

FT245配置说明

D7到D0双向FIFO数据.该总线通常是输入,除非RD＃

为低.

当高,不从FIFO中读取数据.何时

低,有数据可在其中可以是先进先出

通过驱动RD＃低阅读.当RD＃再次变高

RXF＃将始终走高,只有变低,如果再有另

一个字节读取

在复位这个信号引脚为三态,但通过内部200K电阻上拉至

VCCIO.

当高,不写数据到FIFO.

当低,可将数据写入

到FIFO通过选通

WR＃高后低.在复位这个信号引脚为三态,

但通过内部200K电阻上

拉至VCCIO

使当前FIFO数据字节被驱动到

D0 ... D7当RD＃变低.获取下一个FIFO的数据字节

（如果有的话）从接收FIFO缓冲区时RD＃goes高

写入数据字节的D0 ... D7引脚到发送FIFO缓冲器

当WR＃goes从高向低.

发送即时/唤醒信号结合了两种

在一个单一的引脚功能.如果USB是在暂停模式

（PWREN＃= 1）和远程唤醒处于启用

EEPROM中,选通该管脚低会造成设备要求就USB总线简历.通

常情况下,这可以用来唤醒主机PC

在正常操作（PWREN＃= 0）

如果该引脚为低电平在设备

TX缓冲区中的所有数据将被发送出去,

通过USB从驱动程序的下一个批量IN请求,无论以待数据包大小

这可以被用来优化USB传输速度的一些应用

配合这个引脚VCCIO如果不使用

表3.6通道A和通道B FT245型异步FIFO配置的引脚说明

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