DDR4 SODIMM规格说明书：260引脚，8GB内存模块

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"SuperTalent Datasheet-DDR4-SODIMM-F21SB8GS.pdf" 是一份关于DDR4 SODIMM内存模组的技术规格说明书，主要关注260引脚的外形设计和相关电气特性。 DDR4 SODIMM是一种小型双列直插式存储模块，常用于笔记本电脑、嵌入式系统和其他空间有限的设备中。该模块采用260针脚接口，相较于DDR3，其显著的改进在于工作电压的降低，从DDR3的1.5V或1.35V下降到1.2V（VDD），这有助于减少功耗和发热量。同时，数据线的电源电压VDDQ也保持在1.2V的范围内，而辅助电源VPP为2.5V，SPD（Serial Presence Detect）电压则在2.25V至2.75V之间。 DDR4 SDRAM的特性包括16个内部银行，这提升了并发访问的能力，增强了多任务处理性能。此外，它采用了Bank Grouping技术，允许不同或相同Bank组之间的CAS to CAS延迟（tCCD_L, tCCD_S）可调，进一步优化了内存访问效率。数据传输速率支持PC4-2133、PC4-1866和PC4-1600，这些速率对应于DDR4内存的等效频率，例如PC4-2133代表3200MT/s的时钟速度。该内存模组还具备双向差分数据 strobe（Bi-Directional Differential Data Strobe），这种设计提高了数据传输的稳定性和抗干扰能力。8位预取（8-bit prefetch）功能意味着每次从内存芯片读取或写入的数据量是8位，而非DDR3的4位，从而提高了数据吞吐量。Burst Length（BL）可以在运行时动态切换，支持BL8（8次连续突发）和BC4（Burst Chop，4次突发后切换方向）模式，提供了更灵活的内存操作。 DDR4还包括On-Die Termination（ODT）功能，这是一种在内存芯片内部实现的终端电阻，有助于减小信号反射并改善信号完整性。此外，内存模块集成了温度传感器，可以实时监测内存温度，确保系统稳定性。最后，该产品符合RoHS（Restriction of Hazardous Substances，限制有害物质指令），这意味着它不含欧盟法规限制的六种有害物质，符合环保标准。 DDR4 SODIMM F21SB8GS是一款高效、低功耗的内存解决方案，适用于需要高性能和低能耗的现代计算平台。它的各种特性如更低的工作电压、更高的数据传输速率、先进的Bank Grouping和ODT技术，都体现了DDR4相对于前代标准的显著进步。

260-pin SODIMM DDR4 SDRAM

http://www.supertalent.com/oem Products and specifications discussed herein are subject to change without notice

Symbol Type Function

ODT, (ODT1) Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the

DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and

DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in

MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ,

DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be

ignored if MR1 is programmed to disable RTT_NOM.

ACT_n

Input

Activation Command Input: ACT_n defines the Activation command being entered along

with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row

Address A16, A15 and A14.

RAS_n/A16,

CAS_n

A15,

WE_n

A14

Input

Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the

command being entered. Those pins have multifunction. For example, for activation with

ACT_n Low, those are Addressing like A16, A15 and A14 but for non-activation command

with ACT_n High, those are Command pins for Read, Write and other command defined in

command truth table.

DM_n/D

QS_t,

MU_n

/DBI

U_n),

(

ML_n

/DBI

L_n)

Input /

Output

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during a

Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by

Mode Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or TDQS is

enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether

to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output

after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only

supported in x8.

BG0 - BG1 Input

Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or

Precharge command is being applied. BG0 also determines which mode register is to be

accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0.

BA0 - BA1 Input

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. Bank address also determines if the mode register or extended

mode register is to be accessed during a MRS cycle.

A0 - A17 Input

Address Inputs: Provided the row address for ACTIVATE Commands and the column

address for Read/Write commands to select one location out of the memory array in the

respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have

additional functions, see other rows. The address inputs also provide the op-code during

Mode Register Set commands. A17 is only defined for the x4 configuration.

A10 / AP Input

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Auto-precharge should be performed to the accessed bank after the Read/Write

operation. (HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled during a

Precharge command to determine whether the Precharge applies to one bank (A10

LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected

by bank addresses.

A12 / BC_n Input

Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst

chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See

command truth table for details.

RESET_n Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when

RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS

rail to rail signal with DC high and low at 80% and 20% of

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