260-pin SODIMM DDR4 SDRAM
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© 2006 Super Talent Technology, Corporation.
4
Symbol Type Function
ODT, (ODT1) Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and
DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in
MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ,
DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be
ignored if MR1 is programmed to disable RTT_NOM.
ACT_n
Input
Activation Command Input: ACT_n defines the Activation command being entered along
with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row
Address A16, A15 and A14.
RAS_n/A16,
CAS_n
/
A15,
WE_n
/
A14
Input
Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. Those pins have multifunction. For example, for activation with
ACT_n Low, those are Addressing like A16, A15 and A14 but for non-activation command
with ACT_n High, those are Command pins for Read, Write and other command defined in
command truth table.
DM_n/D
BI
n/
TD
QS_t,
(D
MU_n
/DBI
U_n),
(
D
ML_n
/DBI
L_n)
Input /
Output
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
Input data is masked when DM_n is sampled LOW coincident with that input data during a
Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by
Mode Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or TDQS is
enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether
to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output
after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only
supported in x8.
BG0 - BG1 Input
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0.
BA0 - BA1 Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
A0 - A17 Input
Address Inputs: Provided the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions, see other rows. The address inputs also provide the op-code during
Mode Register Set commands. A17 is only defined for the x4 configuration.
A10 / AP Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Auto-precharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
A12 / BC_n Input
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See
command truth table for details.
RESET_n Input
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when
RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS
rail to rail signal with DC high and low at 80% and 20% of
V
DD
.