Altera FFT MegaCore v11.1 用户指南

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"altera_fft_v11.1用户手册，英文版 Altera IP核用户指南，专注于FFT（快速傅里叶变换）在FPGA中的应用" 这篇用户手册详细介绍了Altera公司的FFTMegaCore功能，这是一款专为FPGA设计的高效能、可配置的快速傅里叶变换IP核心。FFTMegaCore是Altera Quartus综合工具的一部分，用于在Cyclone、Arria和Stratix系列FPGA中实现高速、低功耗的数字信号处理应用。用户手册首先会介绍FFT的基本概念，包括傅里叶变换在信号处理和通信系统中的重要性，以及FFT算法如何通过离散傅里叶变换(DFT)的优化来提高计算效率。它将详细阐述不同类型的FFT结构，如Bit-Reverse、Decimation-in-Time (DIT)和Decimation-in-Frequency (DIF)等，并解释如何根据特定的应用需求选择合适的FFT实现。手册接下来会详细描述FFTMegaCore的配置选项，包括FFT的长度、数据位宽、并行度、以及是否支持实时可编程性。用户可以按照需求调整这些参数以优化性能、面积和功耗。此外，手册还将涵盖IP核的输入/输出接口，例如如何连接数据流到IP核，以及如何处理数据对齐和边界条件。在具体实现部分，用户手册会提供详细的步骤指导，包括如何在Quartus设计环境中集成FFTMegaCore，设置工程，以及使用IP核的约束文件。此外，它还会讨论时序分析和综合优化策略，以确保设计满足时钟速度和功耗目标。错误处理和调试是另一个重要的章节，手册将指导用户如何利用Altera的开发工具诊断和解决在设计过程中可能遇到的问题。这可能包括检查波形、查看IP核内部状态，以及利用Altera的IP调试功能。手册还将包含一些实用示例和设计实例，帮助用户快速理解和应用FFTMegaCore。这些例子通常涵盖从简单的单精度浮点FFT到复杂的数据流处理系统。最后，手册将提供详细的参考文献和进一步学习资源，以便用户深入研究FFT算法和FPGA设计。 "altera_fft_v11.1用户手册"是开发者在FPGA中实现高性能FFT应用的宝贵参考资料，无论他们是新手还是经验丰富的工程师。通过深入理解并充分利用该手册，用户能够有效地利用Altera的FFTMegaCore实现各种信号处理任务，从而提升其FPGA设计的性能和效率。

1–8 Chapter 1: About This MegaCore Function

Performance and Resource Utilization

FFT MegaCore Function November 2011 Altera Corporation

User Guide

Stratix III Devices

Table 1–10 lists the streaming data flow performance, using the 4 multipliers/2 adders

complex multiplier structure, for data and twiddle width 16, for Stratix III

(EP3SE50F780C2) devices.

Table 1–11 lists the variable streaming data flow performance, with in order inputs

and bit-reversed outputs, for width 16 (32 for floating point), for Stratix III

(EP3SE50F780C2) devices.

1 The variable streaming with fixed-point number representation uses natural word

growth, therefore the multiplier requirement is larger compared with the equivalent

streaming FFT with the same number of points.

If you want to significantly reduce M9K memory utilization, set a lower f

MAX

target.

1024 Single Output 1 223 5230 23.43 6344 28.42 7279 32.6

4096 Single Output 1 227 24705 108.7 28801 126.73 32898 144.75

256 Single Output 2 235 585 2.49 841 3.58 1098 4.67

1024 Single Output 2 221 2652 12 3676 16.64 4701 21.28

4096 Single Output 2 219 12329 56.28 16495 75.3 20605 94.06

Notes to Ta bl e 1– 9:

(1) In the burst I/O data flow architecture, you can specify the number of engines in the FFT parameter editor. You may choose from one to two

single-output engines in parallel, or from one, two, or four quad-output engines in parallel.

(2) Transform time is the time frame when the input block is loaded until the first output sample (corresponding to the input block) is output.

Transform time does not include the time to unload the full output data block.

(3) Block throughput is defined as the minimum number of cycles between two successive start-of-packet (

sink_sop

) pulses.

Table 1–9. Performance with the Burst Data Flow Architecture—Cyclone III Devices (Part 2 of 2)

Points

Engine

Architecture

Number of

Engines

(1)

fMAX

(MHz)

Transform

Calculation Time

(2)

Data Load & Transform

Calculation

Block Throughput

(3)

Cycles Time (s) Cycles Time (s) Cycles Time (s)

Table 1–10. Performance with the Streaming Data Flow Engine Architecture—Stratix III Devices

Points

Combinational

ALUTs

Logic

Registers

Memory

(Bits)

Memory

(M9K)

18 × 18

Blocks

MAX

(MHz)

Clock

Cycle

Count

Tran sform

Time (s)

256 2094 3715 39168 20 12 442 256 0.58

1024 2480 4458 155904 20 12 413 10024 2.48

4096 2357 4545 622848 76 12 388 4096 10.57

Table 1–11. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix III Devices (Part 1 of 2)

Point Type Points

Combinational

ALUTs

Logic

Registers

Memory

(Bits)

Memory

(M9K)

18 × 18

Blocks

MAX

(MHz)

Clock

Cycle

Count

Transform

Time (s)

Fixed 256 2511 3927 10239 16 20 341 256 0.75

Fixed 1024 3476 5244 42218 23 28 323 1024 3.17

Fixed 4096 4480 6628 170639 42 36 320 4096 12.8

Floating 256 14059 13424 34728 64 48 303 256 0.84

Chapter 1: About This MegaCore Function 1–9

Performance and Resource Utilization

November 2011 Altera Corporation FFT MegaCore Function

User Guide

Table 1–12 lists resource usage with buffered burst data flow architecture, using the

4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,

for Stratix III (EP3SE50F780C2) devices.

Table 1–13 lists performance with buffered burst data flow architecture, using the

4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,

for Stratix III (EP3SE50F780C2) devices.

Floating 1024 18019 16560 140750 95 64 286 1024 3.58

Floating

(1)

4096 22026 19717 568579 150 80 286 4096 14.33

Note to Tab le 1–1 1:

(1) EP3SL70F780C2 device.

Table 1–11. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix III Devices (Part 2 of 2)

Point Type Points

Combinational

ALUTs

Logic

Registers

Memory

(Bits)

Memory

(M9K)

18 × 18

Blocks

MAX

(MHz)

Clock

Cycle

Count

Transform

Time (s)

Table 1–12. Resource Usage with Buffered Burst Data Flow Architecture—Stratix III Devices

Points

Number of

Engines

(1)

Combinational

ALUTs

Logic

Registers

Memory

(Bits)

Memory

(M9K)

18 × 18

Blocks

MAX

(MHz)

256 1 1952 3586 30976 16 12 408

1024 1 1989 3784 123136 16 12 390

4096 1 2031 3968 491776 60 12 382

256 2 3261 5577 30976 31 24 365

1024 2 3306 5785 123136 31 24 369

4096 2 3348 5977 491776 60 24 390

256 4 5712 9971 30976 60 48 341

1024 4 5775 10195 123136 60 48 349

4096 4 5857 10403 491776 60 48 325

Note to Tab le 1–1 2:

(1) When using the buffered burst architecture, you can specify the number of quad-output FFT engines in the FFT parameter editor.

Table 1–13. Performance with the Buffered Burst Data Flow Architecture—Stratix III Devices (Part 1 of 2)

Points

Number of

Engines

(1)

MAX

(MHz))

Transform Calculation

Time

(2)

Data Load & Transform

Calculation

Block Throughput

(3)

Cycles Time (s) Cycles Time (s) Cycles Time (s)

256 1 408 235 0.58 491 1.2 331 0.81

1024 1 390 1069 2.74 2093 5..37 1291 3.31

4096 1 382 5167 13.54 9263 24.27 6157 16.13

256 2 365 162 0.44 397 1.09 299 0.82

1024 2 369 557 1.51 1581 4.29 1163 3.15

4096 2 390 2607 6.68 6703 17.17 5133 13.15

256 4 341 118 0.35 347 1.02 283 0.83

1024 4 349 340 0.98 1364 3.91 1099 3.15

1–10 Chapter 1: About This MegaCore Function

Performance and Resource Utilization

FFT MegaCore Function November 2011 Altera Corporation

User Guide

Table 1–14 lists resource usage with burst data flow architecture, using the

4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,

for Stratix III (EP3SE50F780C2) devices.

4096 4 325 1378 4.25 5474 16.87 4633 14.27

Notes to Ta bl e 1– 13:

(1) When using the buffered burst architecture, you can specify the number of quad-output engines in the FFT parameter editor. You may choose

from one, two, or four quad-output engines in parallel.

(2) In a buffered burst data flow architecture, transform time is defined as the time from when the N-sample input block is loaded until the first

output sample is ready for output. Transform time does not include the additional N-1 clock cycle to unload the full output data block.

(3) Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.

Table 1–13. Performance with the Buffered Burst Data Flow Architecture—Stratix III Devices (Part 2 of 2)

Points

Number of

Engines

(1)

MAX

(MHz))

Transform Calculation

Time

(2)

Data Load & Transform

Calculation

Block Throughput

(3)

Cycles Time (s) Cycles Time (s) Cycles Time (s)

Table 1–14. Resource Usage with the Burst Data Flow Architecture—Stratix III Devices

Points

Engine

Architecture

Number of

Engines

(2)

Combinational

ALUTs

Logic

Registers

Memory

(Bits)

Memory

(M9K)

18 × 18

Blocks

MAX

(MHz)

256 Quad Output 1 1796 3502 14592 8 12 408

1024 Quad Output 1 1830 3686 57600 8 12 429

4096 Quad Output 1 1882 3852 229632 28 12 410

256 Quad Output 2 2968 5489 14592 15 24 382

1024 Quad Output 2 3015 5681 57600 15 24 388

4096 Quad Output 2 3054 5856 229632 28 24 386

256 Quad Output 4 5162 9891 14592 28 48 348

1024 Quad Output 4 5213 10100 57600 28 48 380

4096 Quad Output 4 5283 10290 229632 28 48 367

256 Single Output 1 704 1435 9472 3 4 438

1024 Single Output 1 740 1481 37120 6 4 414

4096 Single Output 1 805 1527 147712 19 4 404

256 Single Output 2 1037 2332 14592 9 8 413

1024 Single Output 2 1050 2408 57600 11 8 402

4096 Single Output 2 1092 2484 229632 28 8 406

Notes to Ta bl e 1– 14:

(1) Represents data and twiddle factor precision.

(2) When using the burst data flow architecture, you can specify the number of engines in the FFT parameter editor. You may choose from one to

two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.

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