System Verilog验证方法学手册

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"Verificatiom Methodology Manual for System Verilog是Synopsys公司推出的一本基于System Verilog的验证方法学手册，可以视为RVM（Reconfigurable Verification Methodology）在System Verilog语言环境下的扩展版本。这本书由Janick Bergeron、Eduard Cerny、Alan Hunter和Andrew Nightingale等人编写，详细介绍了如何使用System Verilog进行高效的集成电路验证工作。" 《Verification Methodology Manual for System Verilog》这本书提供了深入的指导，旨在帮助工程师们理解和应用System Verilog的高级功能来构建可重用和可扩展的验证环境。System Verilog是一种强大的硬件描述语言，不仅支持设计的描述，还特别适用于复杂的验证任务。书中详细讨论了以下关键知识点： 1. **基础概念**：包括System Verilog的基本语法和数据类型，如类、接口、包、任务和函数等，这些都是构建验证环境的基础。 2. **UVM（Universal Verification Methodology）**：虽然VMM（Verification Methodology Manual）不直接涉及UVM，但它是后来UVM发展的重要先驱。UVM是基于System Verilog的业界标准验证方法学，提供了预定义的组件和框架，使得验证更加标准化和高效。 3. **验证计划**：书中详细介绍了如何制定验证计划，包括目标设定、覆盖率度量、验证环境的组织结构以及验证过程的管理。 4. **随机化与约束**：System Verilog的随机化机制和约束系统是其强大之处，书中有专门的章节讲解如何利用这些特性来生成有效的测试激励。 5. **覆盖度量**：书中涵盖了如何定义和跟踪验证覆盖，这对于确保设计的充分验证至关重要。 6. **接口和通信机制**：System Verilog的接口和事件驱动模型使得模块间的通信更加灵活，书中有详尽的示例解释这些概念。 7. **环境构建**：VMM提供了一种框架来组织验证组件，如代理（Agent）、监视器（Monitor）、驱动器（Driver）和断言（Assertion），帮助工程师构建复杂的验证环境。 8. **复用与扩展**：VMM强调验证组件的复用和扩展性，通过类继承和多态性来实现，这使得验证环境的维护和升级变得更加便捷。 9. **案例研究**：书中可能包含实际的案例研究，展示了如何将VMM应用于具体的验证问题，帮助读者更好地理解和应用所学知识。《Verification Methodology Manual for System Verilog》是System Verilog验证领域的重要参考资料，它不仅阐述了验证的基本理念，还提供了实用的方法和技术，帮助工程师提高验证效率，降低集成电路验证的复杂性和风险。

Preface

xvi Verification Methodology Manual for SystemVerilog

Chapter 4 describes the components of a verification environment and how to

implement them. Its companion Appendix A specifies a set of base and utility classes

that are used to implement the generic functionality required by all environments and

components.

Chapter 5 describes how to provide stimulus to the design under verification and how

it can be constrained to create interesting conditions. The generator classes specified

in Appendix A help to rapidly create VMM-compliant generator components.

Chapter 6 describes how to use qualitative metrics to drive the verification process

and using a constrainable random verification environment built using the guidelines

presented in the previous chapters to efficiently implement it.

Chapter 7 describes how assertions can be used with formal technology. Only a subset

of the checkers described in Appendix B can be used within this context.

Chapter 8 describes how the principles presented in the previous chapters can be

leveraged for system-level verification. Its companion Appendix C specifies a

command language and extensible component infrastructure to implement block and

system-level verification environments.

Chapter 9 describes how the integration of a general-purpose programmable

processor in a system can be verified using a set of predefined C functions described

in Appendix D.

The support infrastructure is specified in appendices A through D by describing the

interface and functionality of each element. No implementation is provided. It is up to

each vendor to provide a suitable implementation. This gives the opportunity to EDA

or IP vendors to optimize the implementation of the infrastructure for their particular

platform. It also eliminates the risk that unintended side effects of a particular

"reference" implementation might be interpreted as expected behavior. The code for

the interface specifications is available at the companion Web site:

http://vmm-sv.org

Note that the methodology can be followed without using the support elements

specified in the appendices. Any functionally equivalent set of elements, providing

similar functionality, would work. However, using a different set of support elements

will likely diminish the interoperability of verification components and environments

written using different support infrastructures.

Not for (re)distribution

How to Read this Book

Verification Methodology Manual for SystemVerilog xvii

HOW TO READ THIS BOOK

This book is not designed as a textbook that can be read and applied linearly.

Although the authors have made their best effort to present the material in a logical

order, it will be often difficult to appreciate the importance or wisdom of some

elements of the methodology without a grasp of the overall picture. Unfortunately, it

is not possible to draw an overall picture without first building the various elements

used to construct it.

The chicken-and-egg paradox is inherent to describing methodologies. A

methodology is about taking steps today to make life easier in some future. A

successful methodology will help reduce the overall cost of a project through

investments at earlier stages that will provide greater returns later on. In a practical

description of a methodology, it is difficult to justify some of the initial costs as their

future benefit is not immediately apparent. Similarly, describing the future benefits is

not possible without describing the elements that, when put together, will create these

benefits.

A reader unfamiliar with an equivalent methodology would typically require two

readings of the entire book. A first reading will help form the overall picture of the

methodology, how the various elements fit together and the benefits that can be

realized. A second reading will help appreciate its detailed implementation process

and supporting library.

Although everyone will benefit from reading the entire book, there are sections that

are more relevant to specific verification tasks. Designers must read Chapter 3. They

should also read Chapter 7 if they intend to use formal technology to verify their

design. Verification leaders and project managers should read Chapters 2 and 6.

Verification engineers responsible for the implementation and maintenance of the

verification environment must read Chapters 4 and 5 and should read Chapter 8.

Verification IP developers should read Chapters 4 and 8. Verification engineers

responsible for implementing testcases should read the first half of Chapter 5. If they

are also responsible for implementing functional coverage points, they should read

the second half of Chapter 6. Embedded software verification engineers should read

Chapter 9.

Not for (re)distribution

Preface

xviii Verification Methodology Manual for SystemVerilog

FOR MORE INFORMATION

At the time of writing, SystemVerilog was in the process of being ratified as an IEEE

standard. In addition to several books already—or to be—published, more

information about SystemVerilog can be obtained from:

http://www.eda.org/sv

http://www.eda.org/sv-ieee1800

This book assumes the reader has experience with the entire SystemVerilog language.

It is not designed as an introductory or training text to the verification or assertion

constructs. The following books, listed in alphabetical order, can be used to gain the

necessary experience and knowledge of the language constructs:

Janick Bergeron, "Writing Testbenches Using SystemVerilog", Springer

Ben Cohen, Srinivasan Venkataramanan and Ajeetha Kumari, "SystemVerilog

Assertions Handbook", VhdlCohen Publishing

Chris Spear and Arturo Salz, "SystemVerilog for Verification", Springer

In this book, code examples are provided as extracts that focus on the various points

they are designed to illustrate. It does not contain a full example of the methodology

application within its page. Such an example would consume several tens of pages

filled with SystemVerilog code. It would be difficult to navigate, would become

obsolete as improvements to the methodology are made and impossible to actually

simulate. Pointers to several complete examples and the complete code that includes

the various examples can be found at the companion Web site:

http://vmm-sv.org

The companion Web site will also contain an errata for the latest edition of the book.

It may also publish additional guidelines as the methodology evolves and is

expanded. These additional guidelines will be included in future editions. Discussions

on the use or interpretation of the methodology and suggestions for improvement are

carried in the forums at:

http://verificationguild.com

ACKNOWLEDGEMENTS

The authors would like to thank Holger Keding for his contribution to Chapter 8.

They are also grateful for the thoughtful reviews and challenging comments from

Pierre Aulagnier, Oliver Bell, Michael Benjamin, Jonathan Bradford, Craig Deaton,

Not for (re)distribution

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