FT2232HL：UART到USB转换器的数据手册

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"FT2232HL是一款由Future Technology Devices International Limited（FTDI）公司生产的USB到UART/FIFO接口芯片，常用于实现串口到USB的转换。该芯片支持多种配置，可作为行业标准的串行或并行接口。FT2232HL具有高速USB2.0（480Mbps）和全速USB（12Mbps）兼容性，并且在单芯片上处理完整的USB协议，无需特定的USB固件编程。此外，它还内置了双通道多协议同步串行引擎（MPSSE），简化了同步串行协议的设计，如USB到JTAG、I2C、SPI或bit-bang等。该芯片提供两个独立的UART或FIFO或MPSSE端口，每个端口都有独立的波特率发生器，支持高达12Mbps的RS232/RS422/RS485 UART数据传输速率（RS232速率受限于外部电平）。" FT2232HL芯片是FTDI公司的第五代USB设备，其主要功能是将串行通信（UART）或并行接口转换为USB接口，使得传统串行设备能够通过USB接口与现代计算机进行通信。这个芯片的一大优点在于其高度的灵活性，可以配置为各种行业标准的接口，适应不同应用的需求。芯片内置的USB2.0 High Speed接口支持最高480Mbps的数据传输速度，同时向下兼容USB Full Speed（12Mbps）模式，确保了与广泛使用的USB设备的兼容性。FT2232HL的单芯片解决方案意味着它能处理整个USB协议栈，这减轻了设计者的负担，因为不需要编写特定的USB固件程序。 FT2232HL的独特之处在于其集成的MPSSE功能。MPSSE是Multi-Protocol Synchronous Serial Engine的缩写，可以方便地实现与各种同步串行协议（如JTAG、I2C、SPI）的连接，甚至支持自定义的bit-bang模式，极大地简化了设计复杂度，适用于多种嵌入式系统和测试环境。此外，FT2232HL提供了两个独立的UART或FIFO端口，每个端口都拥有独立的波特率发生器，这意味着用户可以独立设置两个端口的通信速率，以适应不同的设备和应用。对于RS232通信，FT2232HL支持高达12Mbps的数据传输速率，虽然实际RS232的速率受到外部电路电平的影响。 FT2232HL芯片是一个功能强大的USB到UART/FIFO转换器，适用于需要高速、灵活、多协议串行通信的场合，如嵌入式开发、设备调试、工业自动化等领域。其易于配置和丰富的功能使得它成为许多系统设计者首选的接口解决方案。

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.10

Clearance No.: FTDI#77

3.4 Configured Pins

The following sections describe the function of the configurable pins referred to in the table given in

Section 3.2 which is determined by how the FT2232H is configured.

3.4.1 FT2232H pins used in an RS232 interface

The FT2232H channel A or channel B can be configured as an RS232 interface. When configured in this

mode, the pins used and the descriptions of the signals are shown in Table 3.4.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

RS232 Configuration Description

TXD

OUTPUT

TXD = transmitter output

RXD

INPUT

RXD = receiver input

RTS#

OUTPUT

RTS# = Ready To send handshake output

CTS#

INPUT

CTS# = Clear To Send handshake input

DTR#

OUTPUT

DTR# = Data Transmit Ready modem signaling line

DSR#

INPUT

DSR# = Data Set Ready modem signaling line

DCD#

INPUT

DCD# = Data Carrier Detect modem signaling line

RI#

INPUT

RI# = Ring Indicator Control Input. When the Remote Wake

up option is enabled in the EEPROM, taking RI# low can be

used to resume the PC USB Host controller from suspend.

(Also see note 1, 2, 3 in section 4.12)

TXDEN

OUTPUT

TXDEN = (TTL level). For use with RS485 level converters.

RXLED#

OUTPUT

RXLED = Receive signaling output. Pulses low when receiving

data (RXD) via USB. This should be connected to an LED.

TXLED#

OUTPUT

TXLED = Transmit signaling output. Pulses low when

transmitting data (TXD) via USB. This should be connected to

an LED.

Table 3.4 Channel A and Channel B RS232 Configured Pin Descriptions

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.10

Clearance No.: FTDI#77

3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface

The FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.5. To

enter this mode the external EEPROM must be set to make port A 245 mode. A software command (Set

Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel

synchronous FIFO mode. In this mode the „B‟ channel is not available as all resources have been switched

onto channel A. In this mode, data is written or read on the rising edge of the CLKOUT.

Channel A

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

ADBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input unless

OE# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low, there is data

available in the FIFO which can be read by driving RD# low. When in

synchronous mode, data is transferred on every clock that RXF# and

RD# are both low. Note that the OE# pin must be driven low at least

1 clock period before asserting RD# low.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data can be

written into the FIFO by driving WR# low. When in synchronous

mode, data is transferred on every clock that TXE# and WR# are both

low.

RD#

INPUT

Enables the current FIFO data byte to be driven onto D0...D7 when

RD# goes low. The next FIFO data byte (if available) is fetched from

the receive FIFO buffer each CLKOUT cycle until RD# goes high.

WR#

INPUT

Enables the data byte on the D0...D7 pins to be written into the

transmit FIFO buffer when WR# is low. The next FIFO data byte is

written to the transmit FIFO buffer each CLKOUT cycle until WR# goes

high.

CLKOUT

OUTPUT

60 MHz Clock driven from the chip. All signals should be synchronized

to this clock.

OE#

INPUT

Output enable when low to drive data onto D0-7. This should be

driven low at least 1 clock period before driving RD# low to allow for

data buffer turn-around.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two functions on a

single pin. If USB is in suspend mode (PWREN# = 1) and remote

wakeup is enabled in the EEPROM , strobing this pin low will cause the

device to request a resume on the USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low any

data in the device TX buffer will be sent out over USB on the next

Bulk-IN request from the drivers regardless of the pending packet

size. This can be used to optimize USB transfer speed for some

applications. Tie this pin to VCCIO if not used. (Also see note 1, 2, 3

in section 4.12)

Table 3.5 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.4

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.10

Clearance No.: FTDI#77

3.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface

The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.6. To

enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,

data is written or read on the falling edge of the RD# or WR# signals.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input

unless RD# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low,

there is data available in the FIFO which can be read by

driving RD# low. When RD# goes high again RXF# will

always go high and only become low again if there is

another byte to read. During reset this signal pin is tri-

state, but pulled up to VCCIO via an internal 200kΩ

resistor.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data

can be written into the FIFO by strobing WR# high, then

low. During reset this signal pin is tri-state, but pulled up to

VCCIO via an internal 200kΩ resistor.

RD#

INPUT

Enables the current FIFO data byte to be driven onto

D0...D7 when RD# goes low. Fetches the next FIFO data

byte (if available) from the receive FIFO buffer when RD#

goes high.

WR#

INPUT

Writes the data byte on the D0...D7 pins into the transmit

FIFO buffer when WR# goes from high to low.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two

functions on a single pin. If USB is in suspend mode

(PWREN# = 1) and remote wakeup is enabled in the

EEPROM , strobing this pin low will cause the device to

request a resume on the USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is

strobed low any data in the device TX buffer will be sent out

over USB on the next Bulk-IN request from the drivers

regardless of the pending packet size. This can be used to

optimize USB transfer speed for some applications. Tie this

pin to VCCIO if not used. (Also see note 1, 2, 3 in section

4.12)

Table 3.6 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions

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