系统级验证环境设计指南：SystemVerilog测试台实践

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《使用SystemVerilog编写测试台》是一本由Janick Bergeron撰写的专业书籍，它深入探讨了在电子设计自动化（EDA）领域，特别是在验证环境中使用SystemVerilog语言进行测试台设计的最佳实践。SystemVerilog是一种高级硬件描述语言（HDL），专为系统级验证设计而设计，提供了一套强大且灵活的工具，用于构建复杂电路的行为模型。这本书的主要目标是指导读者理解和应用SystemVerilog在测试台（Testbench）设计中的关键概念和技术。它涵盖了测试台设计的基本原则，包括但不限于模块化、一致性、复用性、随机性和覆盖率分析。书中强调了良好的编程风格、信号赋值策略、模拟与行为模型的区别、以及如何利用SystemVerilog的并发性和并发建模特性来模拟真实世界的系统行为。 Bergeron以实际经验者的角度分享了他在设计和调试复杂的数字和混合信号系统时遇到的问题和解决方案，以及如何通过SystemVerilog的高级特性如assertions、覆盖检查和接口描述符（Interface Descriptors，IDF）来确保测试的有效性和可靠性。此外，他还讨论了如何处理边界条件、时序约束、以及如何编写有效的测试用例以达到全面的测试覆盖率。值得注意的是，这本书还特别提到了版权问题，强调所有复制或翻译必须获得Springer Science+Business Media的书面许可，以尊重作者和出版商的知识产权。对于电子化使用，如存储、检索、改编或类似技术，都有严格的限制。《使用SystemVerilog编写测试台》是一本实用性很强的参考书籍，不仅适合已经在SystemVerilog方面有一定基础的工程师，也适合那些希望进入或提升硬件验证技能的初学者，特别是对于理解和实践高级硬件验证技术具有重要的指导意义。在国内，由于有中文版的存在，使得更多的中国工程师能够无障碍地获取和学习这些知识，进一步提升我国电子设计的验证水平。

What This Book Is About

Writing Testbenches using SystemVerilog xvii

These unfamiliar semantics become important in understanding

what makes a well-implemented and robust testbench and in pro-

viding the necessary control and monitor features.

I will also present techniques for applying stimulus and monitoring

the response of a design, by abstracting the physical-level transac-

tions into high-level procedures using bus-functional models. The

architecture of testbenches built around these bus-functional mod-

els is important to create a layer of abstraction relevant to the func-

tion being verified and to minimize development and maintenance

effort. I also show some strategies for making testbenches self-

checking.

Creating random testbenches involves more than calling the $ran-

dom system task. I will show how random stimulus generators,

built on top of bus-functional models, can be architected and

designed to be able to produce the desired stimulus patterns. Ran-

dom generators must be easily externally constrained to increase

the likelihood that a set of interesting patterns will be generated.

Transaction-level modeling is another important concept presented

in this book. It is used to parallelize the implementation and verifi-

cation of a design and to perform more efficient simulations. A

transaction-level model must adequately emulate the functionality

of a design while offering orders of magnitudes in simulation per-

formance over the RTL model. Striking the correct level of accu-

racy is key to achieving that performance improvement.

This book has one large omission: assertions and formal verifica-

tion. It is not that they are not important. SystemVerilog includes

constructs and semantics for writing assertions and coverage prop-

erties using temporal expressions. Formal verification is already an

effective methodology for verifying certain classes of designs. It is

simply a matter of drawing a line somewhere. There are already

books on assertions

or formal verification. This book focuses on

the bread-and-butter of verification for the foreseeable future:

dynamic functional verification using testbenches

1. Cohen, Venkataramanan and Kumari, "SystemVerilog Assertion Hand-

book", VhdlCohen Publishing, 2005

Preface

xviii Writing Testbenches using SystemVerilog

WHAT PRIOR KNOWLEDGE YOU SHOULD HAVE

This book focuses on the functional verification of hardware

designs using SystemVerilog. I expect the reader to have at least a

basic knowledge of VHDL, Verilog, OpenVera or e. Ideally, you

should have experience in writing models and be familiar with run-

ning a simulation using any of the available VHDL or Verilog sim-

ulators. There will be no detailed description of language syntax or

grammar. It may be a good idea to have a copy of a language-

focused textbook or the SystemVerilog Language Reference Manual

as a reference along with this book. I do not describe a synthesiz-

able subset, nor limit the implementation of the verification tech-

niques to using that subset. Verification is a complex task: The

power of the SystemVerilog language will be used to its fullest.

I also expect that you have a basic understanding of digital hard-

ware design. This book uses several hypothetical designs from var-

ious application domains (video, datacom, computing, etc.). How

these designs are actually specified, architected and then imple-

mented is beyond the scope of this book. The content focuses on the

specification, architecture, then implementation of the verification

of these same designs.

Once you are satisfied with the content of this book and wish to put

it in practice, I recommend you pick up a copy of the Verification

Methodology Manual for SystemVerilog

(VMM). It is a book I co-

authored and wrote as a series of very specific guidelines on how to

implement testbenches using SystemVerilog. It uses all of the pow-

erful concepts introduced here. It also includes a set of base classes

that implements generic functionality that every testbench needs.

Why re-invent the wheel? I will refer to the first edition of the

VMM at relevant points in this book where further techniques,

guidelines or support can be found.

READING PATHS

You should really read this book from cover to cover. However, if

you are pressed for time, here are a few suggested paths.

1. Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale,

"Verification Methodology Manual for SystemVerilog", Springer 2005,

ISBN 0-387-25538-9

Preface

xx Writing Testbenches using SystemVerilog

ilog, being a superset of Verilog, benefits from the same smooth ini-

tial learning curve. However—like VHDL—Verilog and

SystemVerilog provide similar concepts: sequential statements, par-

allel constructs, structural constructs and the illusion of parallelism.

These concepts must be learned. Because of its lax requirements,

Verilog lulls the user into a false sense of security. The user believes

that he or she knows the language because there are no syntax

errors or because the simulation results appear to be correct. Over

time, and as a design grows, race conditions and fragile code struc-

tures become apparent, forcing the user to learn these important

concepts. Languages have the same area under the learning curve.

VHDL’s is steeper but Verilog’s goes on for much longer. Some

sections in this book take the reader farther down the Verilog learn-

ing curve.

SystemVerilog continues in Verilog’s footstep. Does that mean that

VHDL is dead? Technically, all VHDL capabilities are directly

available in SystemVerilog. And with the many capabilities avail-

able in SystemVerilog not available in VHDL, there are no longer

any technical reasons to use VHDL

. However, that decision is

never a purely technical one. There will be VHDL legacy code for

years to come. And companies with large VHDL legacies will con-

tinue to use it, if only in a co-simulation capacity. There is also an

effort by the VHDL IEEE Working Group to add these missing

capabilities to VHDL, known as VHDL-200x. Whether or not you

wish—or can afford—to wait for a me too language is again a busi-

ness decision.

Hardware Verification Languages

Hardware verification languages (HVLs) are languages that were

specifically designed to implement testbenches efficiently and pro-

ductively. Commercial solutions include OpenVera from Synopsys

and e from Cadence. Open-source solutions include the SystemC

Verification Library (SCV) from Cadence and Jeda from Juniper

Networks. There are also a plethora of home-grown solutions based

on Perl, SystemC, C++ or TCL. SystemVerilog includes all of the

1. Before anyone paints me as a Verilog bigot, I wish to inform my readers

that I learned VHDL first and have always had a slight preference

toward VHDL over Verilog.

Code Examples

Writing Testbenches using SystemVerilog xxi

features of a hardware verification language. When using System-

Verilog, it is no longer necessary to use a separate language for ver-

ification.

Making use of the verification features of SystemVerilog involves

more than simply learning a new syntax. Although one can con-

tinue to use a Verilog-like directed methodology with SystemVer-

ilog, using it appropriately requires a shift in the way verification is

approached and testbenches are implemented. The directed verifi-

cation strategy used with Verilog is the schematic capture of verifi-

cation. Using SystemVerilog with a constraint-driven random

verification strategy is the synthesis of verification. When used

properly, it is an incredible productivity boost (see Figure 2-16 on

page 56).

Does SystemVerilog mean that OpenVera, e and the other propri-

etary verification and assertion languages are going to die? The

answer is a definite no. SystemVerilog was created by merging

donated features and technologies from proprietary languages. It

did not invent nor create anything new other than integrating these

features and technologies under a consistent syntax and semantics.

The objectives of SystemVerilog are to lower the adoption and

ownership cost of verification tools and to create a broader market-

place through industry-wide support.

SystemVerilog accomplishes these objectives by being an industry

standard. But the problem with industry standards is that they

remain static while the semiconductor technologies continue to

advance. SystemVerilog will more than meet the needs of 90 per-

cent of the users for years to come. But leading edge users, who

have adopted HVLs years ago and are already pushing their limits,

will not be satisfied by SystemVerilog for very long. Proprietary

tools and languages will continue to evolve with those leading edge

projects. Hopefully, their trail-blazing efforts will be folded back

into a future version of SystemVerilog, where their art can become

science.

CODE EXAMPLES

A common complaint I received about the first edition was the lack

of complete examples. You’ll notice that in this book, like the first

two, code samples are still provided only as excerpts. I fundamen-

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