Xilinx SDK：LwIP 1.06a驱动与库文档指南

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"《OS和Libraries Document Collection.pdf》是一份详细的文档集合，由Xilinx公司发布，日期为2013年10月23日。这份文档集专为Xilinx的软件开发提供支持，包括驱动程序、库、板级支持包以及操作系统，旨在帮助开发者构建一个完整的软件平台。文档内容涵盖了Xilinx特定的知识产权和商标，如Virtex、Spartan、ISE等，这些都是Xilinx在美国和其他国家的注册商标，同时也列出了其他公司的相关商标。文档的核心部分是《LibXil Standard CLibraries》，它介绍了针对嵌入式处理器设计的一系列软件库。这些标准库是为简化编程任务而提供的，旨在优化性能和资源管理。Standalone版本（v.3.11.a）作为一个独立的开发平台，提供了独立于硬件的环境，允许用户在没有特定设备支持的情况下进行软件开发和调试。此文档还包括了操作系统相关的文档，但详细信息可能需要参考相应的参考指南，因为这些系统通常有各自独立的完整文档。文档列表提供了方便的索引，只需点击文档名称即可访问详细内容。这份文档集合对于Xilinx用户来说，是开发过程中不可或缺的参考资料，无论是新手还是经验丰富的工程师，都能从中找到所需的技术支持和指导，以提升开发效率和产品质量。"

6 www.xilinx.com UG647 October 23, 2013

MicroBlaze Processor API

void Xil_DCacheInvalidate()

Invalidate the data cache.

If the L2 cache system is present in the hardware, this function invalidates the L2 cache first,

before invalidating the L1 cache.

Note:

For MicroBlaze processors prior to version v7.20.a:

The cache and interrupts are disabled before invalidation starts and restored to their previous state after

invalidation.

void Xil_DCacheInvalidateRange(unsigned int cache_addr,

unsigned int cache_size

Invalidate the data cache. This function can be used for invalidating all or part of the data cache.

The parameter

cache_addr indicates the beginning of the cache location and cache_size

represents the size from

cache_addr to invalidate.

Note that cache lines will be invalidated starting from the cache line to which cache_addr

belongs and ending at the cache line containing the address (

cache_addr +

cache_size - 1).

If the L2 cache system is present in the hardware, this function invalidates the relevant L2

cache range first, before invalidating the L1 cache range.

Note:

For MicroBlaze processors prior to version v7.20.a:

The cache and interrupts are disabled before invalidation starts and restored to their previous state after

invalidation.

For example, Xil_DCacheInvalidateRange (0x00000300, 0x100) invalidates the data

cache region from 0x300 to 0x3ff (0x100 bytes of cache memory is cleared starting from

0x300).

Software Sequence for Initializing Instruction and Data Caches

Typically, before using the cache, your program must perform a particular sequence of cache

operations to ensure that invalid/dirty data in the cache is not being used by the processor. This

would typically happen during repeated program downloads and executions.

The following example snippets show the necessary software sequence for initializing

instruction and data caches in your program.

/* Initialize ICache *//

Xil_ICacheInvalidate ();

Xil_ICacheEnable ();

/* Initialize DCache */

Xil_DCacheInvalidate ();

Xil_DCacheEnable ();

At the end of your program, you should also put in a sequence similar to the example snippet

below. This ensures that the cache and external memory are left in a valid and clean state.

/* Clean up DCache. For writeback caches, the disable_dcache routine

internally does the flush and invalidate. For write through caches,

an explicit invalidation must be performed on the entire cache. */

#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 0

Xil_DCacheInvalidate ();

#endif

Xil_DCacheDisable ();

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MicroBlaze Processor API

UG647 October 23, 2013 www.xilinx.com 7

/* Clean up ICache */

Xil_ICacheInvalidate ();

Xil_ICacheDisable ();

MicroBlaze Processor Fast Simplex Link (FSL) Interface Macros

Standalone includes macros to provide convenient access to accelerators connected to the

MicroBlaze Fast Simplex Link (FSL) Interfaces.

MicroBlaze Processor Fast Simplex Link (FSL) Interface Macro Summary

The following is a list of the available macros. Click on a macro name to go to the description of

the active macros.

MicroBlaze Processor FSL Macro Descriptions

The following macros provide access to all of the functionality of the MicroBlaze FSL feature in

one simple and parameterized interface. Some capabilities are available on MicroBlaze v7.00.a

and later only, as noted in the descriptions.

In the macro descriptions,

val refers to a variable in your program that can be the source or

sink of the FSL operation.

Note:

id must be an integer literal in the basic versions of the macro (getfslx, putfslx,

tgetfslx, tputfslx) and can be an integer literal or an integer variable in the dynamic versions of the

macros (getdfslx, putdfslx, tgetdfslx, tputdfslx.)

You must include fsl.h in your source files to make these macros available.

getfslx(val,id,flags)

Performs a get function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is a literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later). The semantics

of the instruction is determined by the valid FSL macro flags, which are listed in Table 2,

page 9.

putfslx(val,id,flags)

Performs a put function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is a literal in the range of 0 to 7 (0 to 15 for MicroBlaze processor v7.00.a and later).

The semantics of the instruction is determined by the valid FSL macro flags, which are listed in

Table 2, page 9.

tgetfslx(val,id,flags)

Performs a test get function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is a literal in the ranging of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later). This macro can

be used to test reading a single value from the FSL. The semantics of the instruction is

determined by the valid FSL macro flags, which are listed in Table 2, page 9.

getfslx(val,id,flags)

putfslx(val,id,flags)

tgetfslx(val,id,flags)

getd fslx(val,id,flags)

putdfslx(val,id,flags)

tgetdfslx(val,id,flags)

tputdfslx(val,id,flags)

fsl_isinvalid(invalid)

fsl_iserror(error)

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8 www.xilinx.com UG647 October 23, 2013

MicroBlaze Processor API

tputfslx(val,id,flags)

Performs a put function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is a literal in the range of 0 to 7 (0 to 15 for MicroBlaze processor v7.00.a and later). This

macro can be used to test writing a single value to the FSL.The semantics of the put instruction

is determined by the valid FSL macro flags, which are listed in Table 2, page 9.

getd fslx(val,id,flags)

Performs a get function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is an integer value or variable in the range of 0 to 15. The semantics of the instruction is

determined by the valid FSL macro flags, which are listed in Table 2, page 9. This macro is

available on MicroBlaze processor v7.00.a and later only.

putdfslx(val,id,flags)

Performs a put function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is an integer value or variable in the range of 0 to 15. The semantics of the instruction is

determined by the valid FSL macro flags, which are listed in Table 2, page 9. This macro is

available on MicroBlaze processor v7.00.a and later only.

tgetdfslx(val,id,flags)

Performs a test get function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is an integer or variable in the range of 0 to 15. This macro can be used to test reading a

single value from the FSL. The semantics of the instruction is determined by the valid FSL

macro flags, listed in Table 2. This macro is available on MicroBlaze processor v7.00.a and

later only.

tputdfslx(val,id,flags)

Performs a put function on an input FSL of the MicroBlaze processor; id is the FSL identifier

and is an integer or variable in the range of 0 to 15. This macro can be used to test writing a

single value to the FSL.The semantics of the instruction is determined by the valid FSL macro

flags, listed in Table 2. This macro is available on MicroBlaze processor v7.00.a and later only.

fsl_isinvalid(invalid)

Checks if the last FSL operation returned valid data. This macro is applicable after invoking a

non-blocking FSL put or get instruction. If there was no data on the FSL channel on a get, or if

the FSL channel was full on a put,

invalid is set to 1; otherwise, it is set to 0.

fsl_iserror(error)

This macro is used to check if the last FSL operation set an error flag. This macro is applicable

after invoking a control FSL put or get instruction. If the control bit was set

error is set to 1;

otherwise, it is set to 0.

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