Microsemi ProASIC3E Flash FPGA芯片手册详细解析

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ProASIC3E DC and Switching Characteristics

2-2 Revision 13

Table 2-2 • Recommended Operating Conditions

Symbol Parameter Commercial Industrial Units

Ambient temperature 0 to +70 –40 to +85 °C

Junction temperature 0 to +85 –40 to +100 °C

VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode

3.15 to 3.45 3.15 to 3.45 V

Operation

0 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V

VCCI and VMV

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.0 V DC supply voltage

2.7 to 3.6 2.7 to 3.6 V

LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The programming temperature range supported is T

ambient

= 0°C to 85°C.

3. VPUMP can be left floating during normal operation (not programming mode).

4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-13 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.

VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

5. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature T

STG

(°C)

Maximum Operating Junction

Temperature T

(°C)

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2- 2 for device operating

conditions and absolute limits.

ProASIC3E DC and Switching Characteristics

2-4 Revision 13

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper

power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed

brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on

page 2-4 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3E FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3E Flash Family FPGAs

Revision 13 2-5

Thermal Characteristics

Introduction

The temperature variable in Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

= Junction Temperature = T + T

EQ 1

where:

= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = 

* P



= Junction-to-ambient of the package. 

numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is 

and the junction-to-ambient air thermal resistivity is



. The thermal characteristics for 

are shown for two air flow rates. The absolute maximum junction

temperature is 110°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for an 896-pin FBGA package at commercial temperature and in still air.

EQ 2

Temperature and Voltage Derating Factors

Maximum Power Allowed

Max. junction temp. (C) Max. ambient temp. (C)–



(C/W)

---------------------------------------------------------------------------------------------------------------------------------

110C70C–

13.6C/W

----------------------------------- 5.88 W===

Table 2-5 • Package Thermal Resistivities

Package Type Pin Count 



UnitsStill Air 200 ft./min. 500 ft./min.

Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W

484 3.2 20.5 17.0 15.9 C/W

676 3.2 16.4 13.0 12.0 C/W

896 2.4 13.6 10.4 9.4 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T

= 70°C, VCC = 1.425 V)

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 100°C

1.425 0.87 0.92 0.95 1.00 1.02 1.04

1.500 0.83 0.88 0.90 0.95 0.97 0.98

1.575 0.80 0.85 0.87 0.92 0.93 0.95

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