"Stratix GX器件手册1：技术指南和详细信息"

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The Stratix GX Device Handbook, Volume 1 provides detailed information about Altera's Stratix GX devices for users and developers. The handbook covers topics such as device architecture, features, specifications, and design guidelines. It also includes information on device configuration, programming, and debugging. Altera Corporation, known as The Programmable Solutions Company, holds the copyright for the handbook and its contents. The company's logo, specific device designations, and trademarks are identified throughout the handbook. The handbook serves as a valuable resource for individuals working with Altera's Stratix GX devices, offering comprehensive insights and guidance for successful implementation and utilization. For further inquiries or assistance, individuals can contact Altera Corporation directly at their San Jose office or visit their official website. The Stratix GX Device Handbook, Volume 1 serves as a comprehensive guide for users and developers looking to leverage the capabilities of Altera's innovative technologies.

1–4 Altera Corporation

Stratix GX Device Handbook, Volume 1 February 2005

High-Speed I/O Interface Functional Description

High-Speed I/O

Interface

Functional

Description

The Stratix GX device family supports high-speed serial transceiver

blocks with CDR circuitry as well as source-synchronous interfaces. The

channels on the right side of the device use an embedded circuit

dedicated for receiving and transmitting high-speed serial data streams

to and from the system board. These channels are clustered in a

four-channel serial transceiver building block and deliver high-speed

bidirectional point-to-point data transmissions to provide up to

3.1875 Gbps of full-duplex data transmission per channel. The channels

on the left side of the device support source-synchronous data transfers

at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport

technology I/O standards. Figure 1–1 shows the Stratix GX I/O blocks.

The differential source-synchronous serial interface and the high-speed

serial interface are described in the Stratix GX Transceivers chapter of the

Stratix GX Device Handbook, Volume 1.

EP1SGX25D 455 607

EP1SGX25F 607

EP1SGX40D 624

EP1SGX40G 624

Note to Ta b le 1 – 2:

(1) The number of I/O pins listed for each package includes dedicated clock pins and

dedicated fast I/O pins. However, these numbers do not include high-speed or

clock reference pins for high-speed I/O standards.

Table 1–3. Stratix GX FineLine BGA Package Sizes

Dimension 672 Pin 1,020 Pin

Pitch (mm) 1.00 1.00

Area (mm

)

729 1,089

Length

× width (mm × mm) 27 × 27 33 × 33

Table 1–4. Stratix GX Device Speed Grades

Device 672-Pin FineLine BGA 1,020-pin FineLine BGA

EP1SGX10 -5, -6, -7

EP1SGX25 -5, -6, -7 -5, -6, -7

EP1SGX40 -5, -6, -7

Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 2

of 2) Note (1)

Device 672-Pin FineLine BGA 1,020-Pin FineLine BGA

Altera Corporation 1–5

February 2005 Stratix GX Device Handbook, Volume 1

Introduction to the Stratix GX Device Data Sheet

Figure 1–1. Stratix GX I/O Blocks Note (1)

Notes to Figure 1–1:

(1) Figure 1–1 is a top view of the Stratix GX silicon die.

(2) Banks 9 through 12 are enhanced PLL external clock output banks.

(3) If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the

I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.

(4) For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in

Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2.

(5) These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on

reference clocks and receiver input pins (AC coupled).

FPGA Functional

Description

Stratix GX devices contain a two-dimensional row- and column-based

architecture to implement custom logic. A series of column and row

interconnects of varying length and speed provide signal interconnects

between logic array blocks (LABs), memory block structures, and DSP

blocks.

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (3)

I/O Banks 3, 4, 9 & 10 Support

All Single-Ended I/O Standards (2)

I/O Banks 7, 8, 11 & 12 Support

All Single-Ended I/O Standards (2)

I/O Banks 1 and 2 Support All

Single-Ended I/O Standards Except

Differential HSTL Output Clocks,

Differential SSTL-2 Output Clocks,

HSTL Class II, GTL, SSTL-18 Class II,

PCI, PCI-X, and AGP 1

DQST9 DQST8 DQST7 DQST6 DQST5 DQST4 DQST3 DQST2 DQST1 DQST0

PLL5

VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4

VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7

PLL6

DQSB9 DQSB8 DQSB7 DQSB6 DQSB5 DQSB4 DQSB3 DQSB2 DQSB1 DQSB0

910

VREF1B2 VREF2B2 VREF3B2 VREF4B2VREF1B1 VREF2B1 VREF3B1 VREF4B1

PLL1

PLL2

Bank 1

Bank 2

Bank 3 Bank 4

11 12Bank 8 Bank 7

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (3)

PLL7

PLL8

PLL12

PLL11

(4)

I/O Bank 13 (5)

I/O Bank 14 (5)

I/O Bank 17 (5)

I/O Bank 16 (5)

I/O Bank 15 (5)

1.5-V PCML (5)

1–6 Altera Corporation

Stratix GX Device Handbook, Volume 1 February 2005

FPGA Functional Description

The logic array consists of LABs, with 10 logic elements (LEs) in each

LAB. An LE is a small unit of logic providing efficient implementation of

user logic functions. LABs are grouped into rows and columns across the

device.

M512 RAM blocks are simple dual-port memory blocks with 512 bits plus

parity (576 bits). These blocks provide dedicated simple dual-port or

single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are

grouped into columns across the device in between certain LABs.

M4K RAM blocks are true dual-port memory blocks with 4K bits plus

parity (4,608 bits). These blocks provide dedicated true dual-port, simple

dual-port, or single-port memory up to 36-bits wide at up to 291 MHz.

These blocks are grouped into columns across the device in between

certain LABs.

M-RAM blocks are true dual-port memory blocks with 512K bits plus

parity (589,824 bits). These blocks provide dedicated true dual-port,

simple dual-port, or single-port memory up to 144-bits wide at up to

269 MHz. Several M-RAM blocks are located individually or in pairs

within the device’s logic array.

Digital signal processing (DSP) blocks can implement up to either eight

full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit

multipliers, or one full-precision 36 × 36-bit multiplier with add or

subtract features. These blocks also contain 18-bit input shift registers for

digital signal processing applications, including FIR and infinite impulse

response (IIR) filters. DSP blocks are grouped into two columns in each

device.

Each Stratix GX device I/O pin is fed by an I/O element (IOE) located at

the end of LAB rows and columns around the periphery of the device.

I/O pins support numerous single-ended and differential I/O standards.

Each IOE contains a bidirectional I/O buffer and six registers for

registering input, output, and output-enable signals. When used with

dedicated clocks, these registers provide exceptional performance and

interface support with external memory devices such as DDR SDRAM,

FCRAM, ZBT, and QDR SRAM devices.

High-speed serial interface channels support transfers at up to 840 Mbps

using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O

standards.

Figure 1–2 shows an overview of the Stratix GX device.

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