英特尔i7 i5 数据手册卷二：CPU内部结构与寄存器深度解析

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“英特尔i7 i5 数据手册卷二” 这份官方文档是针对英特尔Core™ i7-800和i5-700系列桌面处理器的详细数据手册，主要涵盖第二部分的内容。文档编号为322165-001，发布于2009年9月。这份资料提供了关于CPU内部结构、寄存器定义、继承I/O（Input/Output）定义、Processor Uncore Configuration Register（处理器外围配置寄存器）以及系统地址映射的深入信息。首先，文档中详述了CPU内部寄存器的定义。寄存器是处理器内部用于临时存储数据和指令的基本单元，它们的速度极快，直接影响着CPU的性能。在i7和i5处理器中，有多种不同类型的寄存器，包括通用寄存器、浮点寄存器、控制寄存器等，每个都有特定的用途，例如，通用寄存器用于一般算术和逻辑运算，浮点寄存器处理浮点计算，而控制寄存器则用于控制处理器的状态和操作模式。其次，文档涵盖了继承I/O定义。这涉及到CPU如何与外部设备如硬盘、显卡、网卡等进行通信。I/O端口定义了这些通信的接口标准，确保了数据的正确传输。了解这些定义对于系统开发者和硬件工程师至关重要，因为他们需要根据这些规范来设计和调试主板上的I/O控制器。 Processor Uncore Configuration Register部分揭示了处理器外围组件的配置细节。Uncore包括了CPU核心之外的其他重要组件，如内存控制器、PCI Express控制器、缓存等。这些寄存器允许系统软件或BIOS进行微调，以优化处理器性能或功耗。系统地址映射则描述了处理器如何将虚拟内存地址转换为物理内存地址，这对于理解和优化系统内存管理至关重要。它涉及到页表结构、内存分段和分页机制，这些都是操作系统和高级编程中的基础知识。文档中还强调了法律条款和免责声明，指出英特尔产品不适用于医疗、生命维持、关键控制、安全系统或核设施应用。此外，英特尔保留对任何标记为“保留”或“未定义”的功能或指令的权利，并可能随时更改规格和产品描述而不预先通知。设计者应避免依赖这些未定义的功能，以防止潜在问题。这份数据手册是开发者、系统架构师和硬件爱好者理解i7和i5处理器内部工作原理、优化系统性能和进行故障排查的重要参考资料。通过深入学习，读者可以更好地掌握如何利用这些处理器的特性来提高系统的整体效能。

16 Datasheet, Volume 2

Datasheet, Volume 2 17

Introduction

1 Introduction

This is Volume 2 of the Datasheet for the Intel

Core™ i7-800 and i5-700 desktop

processor series.

The processor contains one or more PCI devices within a single physical component.

The configuration registers for these devices are mapped as devices residing on the PCI

Bus assigned for the processor socket. This document describes these configuration

space registers or device-specific control and status registers (CSRs) only. This

document does NOT include Model Specific Registers (MSRs).

Note: Throughout this document, the Intel

Core™ i7-800 and i5-700 desktop processor

series may be referred to as “processor”.

Note: Througout this document, the Intel

5 series Chipset Platform Controller Hub Platform

Controller Hub is also referred to as “PCH”.

Note: The term “DT” refers to desktop platforms.

1.1 Register Terminology

Registers and register bits are assigned one or more of the following attributes. These

attributes define the behavior of register and the bit(s) that are contained with in. All

bits are set to default values by hard reset. Sticky bits retain their states between hard

resets.

Term Description

Read Only. If a register bit is read only, the hardware sets its state. The bit may be read

by software. Writes to this bit have no effect.

Write Only. The register bit is not implemented as a bit. The write causes some hardware

event to take place.

RWO

Read/Write Once. These bits can be read by software. After reset, these bits can only

be written by software once, after which the bits becomes ‘Read Only’.

RW Read/Write. A register bit with this attribute can be read and written by software.

Read Clear. The bit or bits can be read by software, but the act of reading causes the

value to be cleared.

RCW

Read Clear/Write. A register bit with this attribute will get cleared after the read. The

RW1C

Read/Write 1 Clear. A register bit with this attribute can be read or cleared by software.

In order to clear this bit, a one must be written to it. Writing a zero will have no effect.

RW0C

Read/Write 0 Clear. A register bit with this attribute can be read or cleared by software.

In order to clear this bit, a zero must be written to it. Writing a one will have no effect.

ROS

RO Sticky. These bits can only be read by software, writes have no effect. The value of

the bits is determined by the hardware only. These bits are only re-initialized to their

default value by a PWRGOOD reset.

RWS

R/W Sticky.These bits can be read and written by software. These bits are only re-

initialized to their default value by a PWRGOOD reset.

RW1S

Read/Write 1 Set. A register bit can be either read or set by software. In order to set

this bit, a one must be written to it. Writing a zero to this bit has no effect. Hardware will

clear this bit.

RW0S

Read/Write 0 Set. A register bit can be either read or set by software. In order to set

this bit, a zero must be written to it. Writing a one to this bit has no effect. Hardware will

clear this bit.

RWL

Read/Write/Lock. A register bit with this attribute can be read or written by software.

Hardware or a configuration bit can lock the bit and prevent it from being updated.

Introduction

18 Datasheet, Volume 2

RWO

Read/Write Once. A register bit with this attribute can be written to only once after

power up. After the first write, the bit becomes read only. This attribute is applied on a bit

by bit basis. For example, if the RWO attribute is applied to a 2-bit field, and only one bit

is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of the

field, may still be written once. This is special case of RWL.

RWDS

RW and Sticky. Re-initialized to default value only with POWERGOOD reset. Value

written will take effect on the next Link layer init.

RRW

Read/Restricted Write. This bit can be read and written by software. However, only

supported values will be written. Writes of non supported values will have no effect.

L Lock. A register bit with this attribute becomes Read Only after a lock bit is set.

RSVD/RV

Reserved Bit. This bit is reserved for future expansion and must not be written. The

latest version of the PCI Local Bus Specification, requires that reserved bits must be

preserved. Any software that modifies a register that contains a reserved bit is

responsible for reading the register, modifying the desired bits, and writing back the

result.

Reserved Bits

Some of the processor registers described in this section contain reserved bits. These bits

are labeled “Reserved”. Software must deal correctly with fields that are reserved. On

reads, software must use appropriate masks to extract the defined bits and not rely on

reserved bits being any particular value. On writes, software must ensure that the values

of reserved bit positions are preserved. That is, the values of reserved bit positions must

first be read, merged with the new values for other bit positions and then written back.

Note that software does not need to perform a read-merge-write operation for the

Configuration Address (CONFIG_ADDRESS) register.

Reserved

Registers

In addition to reserved bits within a register, the processor contains address locations in

the configuration space that are marked either “Reserved” or “Intel Reserved”. The

processor responds to accesses to “Reserved” address locations by completing the host

cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved”

registers can be 8, 16, or 32 bits in size). Writes to “Reserved” registers have no effect on

the processor. Registers that are ®marked as “Intel Reserved” must not be modified by

system software. Writes to “Intel Reserved” registers may cause system failure. Reads to

“Intel Reserved” registers may return a non-zero value.

Default Value

upon a Reset

Upon a reset, the processor sets all of its internal configuration registers to predetermined

default states. Some register values at reset are determined by external strapping

options. The default state represents the minimum functionality feature set required to

successfully bring up the system. Hence, it does not represent the optimal system

configuration. It is the responsibility of the system initialization software (usually BIOS) to

properly determine the DRAM configurations, operating parameters and optional system

features that are applicable, and to program the processor registers accordingly.

“ST” appended to

the end of a bit

name

The bit is “sticky” or unchanged by a hard reset. These bits can only be cleared by a

PWRGOOD reset.

Term Description

Datasheet, Volume 2 19

Configuration Process and Registers

2 Configuration Process and

Registers

2.1 Platform Configuration Structure

The DMI physically connects the processor and the Intel Platform Controller Hub (PCH).

From a configuration standpoint, the DMI is logically PCI Bus 0. A physical PCI Bus 0

does not exist. DMI and the internal devices in the processor Integrated I/O (IIO) and

Intel PCH logically constitute PCI Bus 0 to configuration software. As a result, all

devices internal to the processor and the Intel PCH appear to be on PCI Bus 0.

The system primary PCI expansion bus is physically attached to the Intel PCH and,

from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-

PCI bridge and, therefore, has a programmable PCI Bus number. The PCI Express*

Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI

bridge that is a device resident on PCI Bus 0.

Devices residing in the Processor Uncore appear on PCI Bus FFh. There is a

programmable base bus number that determines the top bus number to start top down

processor socket to PCI bus mapping. The processors default to 255 as the top bus

number. However, this top bus number can be redefined by the SAD_PCIEXBAR CSR

(Bus: FFh, Device 0, Function 1, Register offset 50h).

2.1.1 Processor Integrated I/O (IIO) Devices (PCI Bus 0)

The processor IIO contains the following PCI devices within a single, physical

component. The configuration registers for the devices are mapped as devices residing

on PCI Bus 0.

• Device 0 — DMI Root Port. Logically this appears as a PCI device residing on PCI

Bus 0. Device 0 contains the standard PCI header registers, extended PCI

configuration registers and DMI device specific configuration registers.

• Device 3 — PCI Express Root Port 1. Logically this appears as a “virtual” PCI-to-

PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local Bus

Specification Revision 1.0. Device 3 contains the standard PCI Express/PCI

configuration registers including PCI Express Memory Address Mapping registers. It

also contains the extended PCI Express configuration space that includes PCI

Express error status/control registers and Isochronous and Virtual Channel

controls.

• Device 5 — PCI Express Root Port 3. Logically this appears as a “virtual” PCI-to-

PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus

Specification Revision 1.0. Device 5 contains the standard PCI Express/PCI

configuration registers including PCI Express Memory Address Mapping registers. It

also contains the extended PCI Express configuration space that include PCI

Express error status/control registers and Isochronous and Virtual Channel

controls.

• Device 8 — Integrated I/O Core. This device contains the Standard PCI registers

for each of its functions. This device implements four functions; Function 0 contains

Address Mapping, Intel

Virtualization Technology (Intel

VT) for Directed I/O

(Intel VT-d) related registers and other system management registers. Function 1

contains Semaphore and Scratchpad registers, Function 3 contains System

Configuration Process and Registers

20 Datasheet, Volume 2

Control/Status registers and Function 4 contains miscellaneous control/status

registers on power management and throttling.

• Device 16 — Intel

QuickPath Interconnect. Device 16, Function 0 contains the

Intel

QuickPath Interconnect configuration registers for Intel QuickPath

Interconnect Link. Device 16, Function 1 contains the routing and protocol.

2.1.2 Processor Uncore Devices (PCI Bus — FFh)

The processor Uncore contains the following devices within a single, physical

component. The configuration registers for these devices are mapped as devices

residing on the PCI bus assigned for the processor socket. Bus number is derived by

the maximum bus range setting and processor socket number.

• Device 0 — Generic processor non-core. Device 0, Function 0 contains the generic

non-core configuration registers for the processor and resides at DID (Device ID) of

2C50-7h. Device 0, Function 1 contains the System Address Decode registers and

resides at DID of 2C81h.

• Device 2 — Intel QuickPath Interconnect. Device 2, Function 0 contains the Intel

QuickPath Interconnect configuration registers for Intel QuickPath Interconnect

Link 0 and resides at DID of 2C90h. Device 2, Function 1 contains the physical layer

registers for Intel QuickPath Interconnect Link 0 and resides at DID of 2C91h.

• Device 3 — Integrated Memory Controller. Device 3, Function 0 contains the

general registers for the Integrated Memory Controller and resides at DID of

2C98h. Device 3, Function 1 contains the Target Address Decode registers for the

Integrated Memory Controller and resides at DID of 2C99h. Device 3, Function 4

contains the test registers for the Integrated Memory Controller and resides at DID

of 2C9C.

• Device 4 — Integrated Memory Controller Channel 0. Device 4, Function 0

contains the control registers for Integrated Memory Controller Channel 0 and

resides at DID of 2CA0h. Device 4, Function 1 contains the address registers for

Integrated Memory Controller Channel 0 and resides at DID of 2CA1h. Device 4,

Function 2 contains the rank registers for Integrated Memory Controller Channel 0

and resides at DID of 2CA2h. Device 4, Function 3 contains the thermal control

registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA3h.

• Device 5 — Integrated Memory Controller Channel 1. Device 5, Function 0

contains the control registers for Integrated Memory Controller Channel 1 and

resides at DID of 2CA8h. Device 5, Function 1 contains the address registers for

Integrated Memory Controller Channel 1 and resides at DID of 2CA9h. Device 5,

Function 2 contains the rank registers for Integrated Memory Controller Channel 1

and resides at DID of 2CAAh. Device 5, Function 3 contains the thermal control

registers for Integrated Memory Controller Channel 1 and resides at DID of 2CABh.

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