LMK04208: 双环PLL低噪声时钟消除器技术文档

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"TI-LMK04208.pdf 是一款由TI公司推出的低噪声时钟抖动消除器，型号为LMK04208。该器件具有双环路PLLatinum™锁相环(PLL)架构，适用于需要高精度时钟信号的系统，如FPGA、ADC、DAC等应用。其主要特点包括超低的均方根值(RMS)抖动性能，以及多种功能丰富的时钟管理特性。 1. **超低RMS抖动性能** LMK04208提供出色的时钟稳定性和精度，其RMS抖动性能在12kHz至20MHz的频段下可达到111fs，而在100Hz至20MHz的频段下则为123fs。这种低抖动性能对于数据传输和信号处理应用至关重要，因为它直接影响到系统的整体性能和误码率。 2. **双环路PLL架构** 设备包含两个独立的PLL环路，PLL1和PLL2。PLL1集成了低噪声晶体振荡器电路，并在输入时钟丢失时进入保持模式，同时支持自动或手动的触发和恢复操作。PLL2则提供了标准的低噪声PLL性能，其相位检测器速率高达155MHz，并且有一个OSCin倍频器。 3. **冗余输入时钟与自动切换** LMK04208设计有两个具有丢失信号指示器(LOS)的冗余输入时钟，能够在输入时钟出现故障时自动或手动切换到备用时钟源，增强了系统可靠性。 4. **灵活的输出分配** 提供50%占空比的输出分配，支持从1到1045的输出频率选择，涵盖了偶数和奇数频率，这使得该器件能够适应各种不同的系统需求。 5. **LVPECL输出** 具有6个低电压正射极耦合逻辑(LVPECL)输出，这种高速、低功耗的输出接口适合高速数字系统中的时钟分配。 6. **其他功能** LMK04208还集成了一个精密时钟调理器，可以连接到诸如LMX2582这样的外部PLL+VCO，以增强系统灵活性。此外，它还提供了一个备份参考时钟，用于系统在主时钟失效时的应急工作。 7. **应用领域** LMK04208广泛应用于通信系统、数据中心、测试与测量设备、航空航天和国防等领域，确保这些系统拥有高质量、低抖动的时钟信号。请注意，产品手册中还包含了关于可用性、保修、安全关键应用的使用、知识产权事项和其他重要免责声明的信息。欲了解更多技术文档、工具软件、支持和社区资源，请参阅TI官方网站的相关部分。"

LMK04208

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7 Parameter Measurement Information

7.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V

CPout

= V

- ΔV

I2 = Charge Pump Sink Current at V

CPout

= V

I3 = Charge Pump Sink Current at V

CPout

= ΔV

I4 = Charge Pump Source Current at V

CPout

= V

- ΔV

I5 = Charge Pump Source Current at V

CPout

= V

I6 = Charge Pump Source Current at V

CPout

= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage

7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch

7.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature

GND

= | V

- V

= 2·V

Definition V

Definition for Output

Non-Inverting Clock

Inverting Clock

2·V

GND

= | V

- V

= 2·V

Definition V

Definition for Input

Non-Inverting Clock

Inverting Clock

2·V

LMK04208

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7.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading datasheets or communicating with other engineers. This section will address the measurement and

description of a differential signal so that the reader will be able to understand and discern between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and non-inverting signal. The symbol for this first measurement is typically V

or V

depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal

with respect to the inverting signal. The symbol for this second measurement is V

and is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V

can be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V

as described in the first description.

Figure 8 illustrates the two different definitions side-by-side for inputs and Figure 9 illustrates the two different

definitions side-by-side for outputs. The V

and V

definitions show V

and V

DC levels that the non-inverting

and inverting signals toggle between with respect to ground. V

input and output definitions show that if the

inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now

increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

and V

are often defined as volts (V) and V

is often defined as volts peak-to-peak (V

Figure 8. Two Different Definitions for Differential Input Signals

Figure 9. Two Different Definitions for Differential Output Signals

See AN-912, Common Data Transmission Parameters and their Definitions SNLA036, for more information.

LMK04208

ZHCSFH1 –SEPTEMBER 2016

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8 Detailed Description

8.1 Overview

In default mode of operation, dual PLL mode with internal VCO, the Phase Frequency Detector in PLL1

compares the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external

VCXO or crystal attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1

should be narrow to provide an ultra clean reference clock from the external VCXO or crystal to the

OSCin/OSCin* pins for PLL2.

The Phase Frequency Detector in PLL2 compares the external VCXO or crystal to the internal VCO after the

reference and feedback dividers. The VCXO or crystal on the OSCin input is divided by PLL2 R divider. The

feedback from the internal VCO is divided by the PLL2 Prescaler, the PLL2 N divider, and optionally the VCO

divider.

The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of

the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is

also placed on the distribution path for the Clock Distribution section. The clock distribution consists of 6 outputs.

Each clock output allows the user to select a divide value, a digital delay value, and an analog delay. The 6 clock

outputs drive programmable output buffers. Two clock outputs allow their input signal to be from the OSCin port

directly.

When a 0-delay mode is used, a clock output will be passed through the feedback mux to the PLL1 N Divider for

synchronization and 0-delay.

When an external VCO mode is used, the Fin port will be used to input an external VCO signal. PLL2 Phase

comparison will now be with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may

not be used. One less clock input is available when using an external VCO mode.

When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.

8.1.1 System Architecture

The dual loop PLL architecture of the LMK04208 provides the lowest jitter performance over the widest range of

output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external

reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise

reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop

bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the

same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated

along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to

200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase

noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or

tunable crystal.

Ultra low jitter is achieved by allowing the external VCXO or crystal’s phase noise to dominate the final output

phase noise at low offset frequencies and the internal (or external) VCO’s phase noise to dominate the final

output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

The LMK04208 allows subsets of the device to be used to increase the flexibility of device. These different

modes are selected using MODE: Device Mode. For instance:

• Dual Loop Mode - Typical use case of LMK04208. CLKinX used as reference input to PLL1, OSCin port is

connected to VCXO or tunable crystal.

• Single Loop Mode - Powers down PLL1. OSCin port is used as reference input.

• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and

analog delay.

See Device Functional Modes for more information on these modes.

LMK04208

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Overview (continued)

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)

The LMK04208 has two reference clock inputs for PLL1: CLKin0 and CLKin1. Ref Mux selects CLKin0 or

CLKin1. Automatic or manual switching occurs between the inputs.

CLKin0 and CLKin1 each have input dividers. The input divider allows different clock input frequencies to be

normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching. By

programming these dividers such that the frequency presented to the input of the PLL1 R divider is the same

prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another

CLKin port with a different frequency.

CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).

Fast manual switching between reference clocks is possible with external pins Status_CLKin0 and

Status_CLKin1.

8.1.3 PLL1 Tunable Crystal Support

The LMK04208 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to

perform jitter cleaning.

The LMK04208 must be programmed to enable Crystal mode.

8.1.4 VCXO/Crystal Buffered Output

The LMK04208 provides a dedicated output, OSCout, which is a buffered copy of the PLL2 reference input (see

Functional Block Diagram for a block diagram of this implementation). The PLL2 reference input is typically a low

noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as

microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04208 is programmed. See Clock Output

Synchronization and MODE: Device Mode for further reference of these outputs

The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

The dedicated output buffer OSCout can output frequency lower than the VCXO or Crystal frequency by

programming the OSC Divider. The OSC Divider value range is 2 to 8.

Two clock outputs can also be programmed to be driven by OSCin. This allows a total of 2 additional differential

outputs to be buffered outputs of OSCin. When programmed in this way, a total of 3 differential or 6 single-ended

outputs can be driven by a buffered copy of OSCin.

VCXO/Crystal buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion of

SYNC will still cause these outputs to become low temporarily. Since these outputs will turn off and on

asynchronously with respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur

on the buffered clock outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX bits are set

these outputs will not be affected by the SYNC event except that the phase relationship will change with the

other synchronized clocks unless a buffered clock output is used as a qualification clock during SYNC.

8.1.5 Frequency Holdover

The LMK04208 supports holdover operation to keep the clock outputs on frequency with minimum drift when the

reference is lost until a valid reference clock signal is re-established.

8.1.6 Integrated Loop Filter Poles

The LMK04208 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and

capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter

response. The integrated programmable resistors and capacitors compliment external components mounted near

the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

LMK04208

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Overview (continued)

8.1.7 Internal VCO

The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or

a divided version of the VCO for the Clock Distribution Path. This same selection is also fed back to the PLL2

phase detector through a prescaler and N-divider.

The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd

divide values.

The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.

8.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04208. An external VCO may be

needed to meet stringent output phase noise/jitter requirements in some applications, such as multi-carrier GSM.

An external VCO is permitted in single PLL, dual PLL, or 0-delay dual PLL mode. In 0-delay dual PLL mode, the

clock outputs driven from the external VCO can have deterministic phase with the clock input.

Using an external VCO reduces the number of available clock inputs by one. The VCO divider cannot be used

with an external VCO.

8.1.9 Clock Distribution

The LMK04208 features a total of 6 differential outputs driven from the internal or external VCO.

All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or

LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 12

outputs are available.

If the buffered OSCin output OSCout is included in the total number of clock outputs the LMK04208 is able to

distribute, then up to 7 differential clocks or up to 14 single-ended clocks may be generated with the LMK04208.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.9.1 CLKout DIVIDER

Each clock has a single clock output divider. The divider supports a divide range of 1 to 1045 (even and odd)

with 50% output duty cycle. When divides of 26 or greater are used, the divider/delay block uses extended mode.

The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in

normal mode instead of extended mode. This can result in a small current saving if enabling the VCO Divider

allows 3 or more clock output divides to change from extended to normal mode.

8.1.9.2 CLKout Delay

See Clock Distribution section for details on both a fine (analog) and coarse (digital) delay for phase adjustment

of the clock outputs.

The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the

analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,

glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the

minimum-ensured maximum output frequency of 1536 MHz.

The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in

normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the

period of the clock distribution path by using the CLKoutX_HS bit provided the output divide value is greater than

1. For example, a 2-GHz VCO frequency without the use of the VCO divider results in 250 ps coarse tuning

steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

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