TI AM3892官方ARM Cortex-A8处理器技术手册：高清视频与多媒体功能

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AM3892是一款由 Texas Instruments (TI) 公司推出的专为开发人员设计的高性能 Sitara™ ARM Cortex-A8架构微处理器。这本技术手册是官方文档，旨在提供详细的技术细节和规格，以便工程师们充分理解和利用这款CPU的优势。该芯片的主要特点包括： 1. **多核架构**：AM3892配备了1个16/24/30位以及1个16位的通道，支持并行处理，提高了数据传输效率。 2. **高性能处理器**：基于ARM Cortex-A8 RISC内核，这款微处理器具备强大的计算能力，可实现高效的系统控制和多媒体应用。 3. **视频处理能力**：AM3892支持高级视频处理功能，如扫描、格式转换和速率调整，适用于需要高质量视频输出的场景，如数字HDMI 1.3接口，最高支持165-MHz像素时钟，同时支持HDCP（High-Definition Content Protection）加密。 4. **高速内存接口**：支持双32位 DDR2/3 SDRAM接口，最大可达DDR2-800和DDR3-1600的速度，这对于处理大量数据和高速内存访问至关重要。 5. **多媒体加速**：内置NEON多媒体架构，提供了丰富的浮点运算能力和VFPv3-IEEE754标准兼容性，支持八个8x8设备，适合于图形和音频处理任务。 6. **Jazelle RCT执行环境**：提供了Java技术的运行环境，使得Java应用程序能够在硬件层面上获得优化，提升性能。 7. **内存管理**：拥有动态内存管理系统（DMM），以及可编程的多区内存映射和交错，允许灵活地分配和管理内存资源，提高系统效率。 8. **高效缓存**：配备32KB的指令和数据缓存，有助于减少访问延迟，确保快速响应。通过这些特性，AM3892不仅适合于嵌入式系统、工业自动化、消费电子和多媒体应用等领域，还可以在需要高性能计算和多媒体处理能力的场景中发挥关键作用。开发人员在使用这款处理器时，需要关注其核心架构、内存配置和外设支持，以充分发挥其性能潜力。同时，由于文档强调仅供开发者参考，确保遵循官方指导，正确地进行软硬件协同设计和优化，以实现最佳性能。

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2.8 SGX530 (AM3894 only)

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications.

The SGX530 graphics accelerator efficiently processes a number of various multimedia data types

concurrently:

• Pixel data

• Vertex data

• Video data.

This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning

enabling zero overhead task switching.

The SGX530 has the following major features:

• Vector graphics and 3D graphics.

• Tile-based architecture.

• Universal Scalable Shader Engine ( USSE™) - multi-threaded engine incorporating pixel and vertex

shader functionality.

• Advanced shader feature set - in excess of Microsoft

VS3.0, PS3.0, and OpenGL 2.0.

• Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1.

• Fine-grained task switching, load balancing, and power management.

• Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction.

• Programmable high-quality image anti-aliasing.

• POWERVR™ SGX core MMU for address translation from the core virtual address to the external

physical address (up to 4GB address range).

• Fully-virtualized memory addressing for OS operation in a unified memory architecture.

• Advanced and standard 2D operations [e.g., vector graphics, block level transfers (BLTs), raster

operations (ROPs)].

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2.9 Memory Map Summary

The device has multiple on-chip memories associated with its processors and various subsystems. To

help simplify software development a unified memory map is used where possible to maintain a consistent

view of device resources across all bus masters.

The device system memory mapping is broken into four 1-GB quadrants for target address spaces

allocation. The four quadrants are labeled Q0, Q1, Q2 and Q3 for a total of 4-GB 32-bit address space.

(HDVPSS includes a thirty-third address bit for an additional 4GB of address range; this is for virtual

addressing and not physical memory addressing.) Inside each quadrant, system targets are mapped on

4-MB boundary (except EDMA targets which are decreased to 1-MB regions).

2.9.1 L3 Memory Map

The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure.

The NoC uses an internal packet-based protocol for forward (read command, write command with data

payload) and backward (read response with data payload, write response) transactions. All exposed

interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference

standard.

Table 2-16 shows the general device level-3 (L3) memory map. The table represents the physical

addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM)

may re-map these targets to different virtual addresses through an internal or external MMU. Processors

without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all

masters have access to all L3 regions, but only those with defined connectivity, as shown in . For a list of

the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 5.2. The L3

interconnect returns an address-hole error if any initiator attempts to access a target to which it has no

connection.

Table 2-16. L3 Memory Map

START ADDRESS END ADDRESS

QUAD BLOCK NAME SIZE DESCRIPTION

(HEX) (HEX)

Q0 GPMC 0x0000 0000 0x1FFF FFFF 512MB GPMC

Q0 PCIe Gen2 0x2000 0000 0x2FFF FFFF 256MB PCIe Gen2 Targets

Q0 Reserved 0x3000 0000 0x3FFF FFFF 256MB Reserved

Q1 Reserved 0x4000 0000 0x402F FFFF 3MB Reserved

Q1 L3 OCMC0 0x4030 0000 0x4033 FFFF 256KB OCMC SRAM

Q1 Reserved 0x4034 0000 0x403F FFFF 768KB Reserved (OCMC RAM0)

Q1 L3 OCMC1 0x4040 0000 0x4043 FFFF 256KB OCMC SRAM

Q1 Reserved 0x4044 0000 0x404F FFFF 768KB Reserved (OCMC RAM1)

Q1 Reserved 0x4050 0000 0x407F FFFF 3MB Reserved

Q1 Reserved 0x4080 0000 0x4083 FFFF 256KB Reserved

Q1 Reserved 0x4084 0000 0x40DF FFFF 5888KB Reserved

Q1 Reserved 0x40E0 0000 0x40E0 7FFF 32KB Reserved

Q1 Reserved 0x40E0 8000 0x40EF FFFF 992KB Reserved

Q1 Reserved 0x40F0 0000 0x40F0 7FFF 32KB Reserved

Q1 Reserved 0x40F0 8000 0x40FF FFFF 992KB Reserved

Q1 Reserved 0x4100 0000 0x41FF FFFF 16MB Reserved

Q1 Reserved 0x4200 0000 0x43FF FFFF 32MB Reserved

Q1 L3 CFG Regs 0x4400 0000 0x44BF FFFF 12MB L3 configuration registers

Q1 Reserved 0x44C0 0000 0x45FF FFFF 20MB Reserved

Q1 McASP0 0x4600 0000 0x463F FFFF 4MB McASP0

Q1 McASP1 0x4640 0000 0x467F FFFF 4MB McASP1

Q1 McASP2 0x4680 0000 0x46BF FFFF 4MB McASP2

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Table 2-16. L3 Memory Map (continued)

START ADDRESS END ADDRESS

QUAD BLOCK NAME SIZE DESCRIPTION

(HEX) (HEX)

Q1 HDMI 1.3 Tx 0x46C0 0000 0x46FF FFFF 4MB HDMI 1.3 Tx

Q1 McBSP 0x4700 0000 0x473F FFFF 4MB McBSP

Q1 USB2.0 0x4740 0000 0x477F FFFF 4MB USB2.0 Registers / CPPI

Q1 Reserved 0x4780 0000 0x47BF FFFF 4MB Reserved

Q1 L4 Firewall domain 0x47C0 0000 0x47FF FFFF 4MB Firewall Configuration domain (see

Table 2-19)

Q1 L4 Standard domain 0x4800 0000 0x48FF FFFF 16MB Standard Peripheral domain (see

Table 2-17)

Q1 EDMA TPCC 0x4900 0000 0x490F FFFF 1MB EDMA TPCC Registers

Q1 Reserved 0x4910 0000 0x497F FFFF 7MB Reserved

Q1 EDMA TPTC0 0x4980 0000 0x498F FFFF 1MB EDMA TPTC0 Registers

Q1 EDMA TPTC1 0x4990 0000 0x499F FFFF 1MB EDMA TPTC1 Registers

Q1 EDMA TPTC2 0x49A0 0000 0x49AF FFFF 1MB EDMA TPTC2 Registers

Q1 EDMA TPTC3 0x49B0 0000 0x49BF FFFF 1MB EDMA TPTC3 Registers

Q1 Reserved 0x49C0 0000 0x49FF FFFF 4MB Reserved

Q1 L4 High-Speed 0x4A00 0000 0x4AFF FFFF 16MB High-Speed Peripheral domain (see

Domain Table 2-18)

Q1 Instrumentation 0x4B00 0000 0x4BFF FFFF 16MB EMU Subsystem region

Q1 DDR EMIF0 0x4C00 0000 0x4CFF FFFF 16MB Configuration registers

registers

(1)

Q1 DDR EMIF1 0x4D00 0000 0x4DFF FFFF 16MB Configuration registers

registers

(1)

Q1 DDR DMM 0x4E00 0000 0x4FFF FFFF 32MB Configuration registers

Registers

(1)

Q1 GPMC Registers 0x5000 0000 0x50FF FFFF 16MB Configuration registers

Q1 PCIe Gen2 Registers 0x5100 0000 0x51FF FFFF 16MB Configuration registers

Q1 Reserved 0x5200 0000 0x54FF FFFF 48MB Reserved

Q1 Reserved 0x5500 0000 0x55FF FFFF 16MB Reserved

Q1 SGX530 0x5600 0000 0x56FF FFFF 16MB SGX530 Slave Port

AM3894 only)

Q1 Reserved 0x5600 0000 0x56FF FFFF 16MB Reserved

(AM3892 only)

Q1 Reserved 0x5700 0000 0x57FF FFFF 16MB Reserved

Q1 Reserved 0x5800 0000 0x5BFF FFFF 64MB Reserved

Q1 Reserved 0x5C00 0000 0x5DFF FFFF 32MB Reserved

Q1 Reserved 0x5E00 0000 0x5FFF FFFF 32MB Reserved

Q1 Tiler 0x6000 0000 0x7FFF FFFF 512MB Virtual Tiled Address Space

Q DDR EMIF0/1 0x8000 0000 0xBFFF FFFF 1GB DDR

SDRAM

(2)

Q3 DDR EMIF0/1 0xC000 0000 0xFFFF FFFF 1GB DDR

SDRAM

(2)

Q4-7 DDR DMM 0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM Tiler Extended address map –

Virtual Views (HDVPSS only)

(1) These accesses occur through the DDR DMM Tiler Ports. The DMM will split address ranges internally to address DDR EMIF and DDR

DMM control registers.

(2) DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM. See the

DDR DMM documentation for more details.

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2.9.2 L4 Memory Map

2.9.2.1 L4 Standard Peripheral

The L4 standard peripheral bus accesses standard peripherals and IP configuration registers. The

memory map is shown in Table 2-17.

Table 2-17. L4 Standard Peripheral Memory Map

START ADDRESS

DEVICE NAME END ADDRESS (HEX) SIZE DESCRIPTION

(HEX)

L4 Standard 0x4800 0000 0x4800 07FF 2KB Address/Protection (AP)

Configuration

0x4800 0800 0x4800 0FFF 2KB Link Agent (LA)

0x4800 1000 0x4800 13FF 1KB Initiator Port (IP0)

0x4800 1400 0x4800 17FF 1KB Initiator Port (IP1)

0x4800 1800 0x4800 1FFF 2KB Reserved (IP2 – IP3)

Reserved 0x4800 2000 0x4800 7FFF 24KB Reserved

e-Fuse Controller 0x4800 8000 0x4800 8FFF 4KB Peripheral Registers

0x4800 9000 0x4800 9FFF 4KB Support Registers

Reserved 0x4800 A000 0x4800 FFFF 24KB Reserved

Reserved 0x4801 2000 0x4801 FFFF 56KB Reserved

UART0 0x4802 0000 0x4802 0FFF 4KB Peripheral Registers

0x4802 1000 0x4802 1FFF 4KB Support Registers

UART1 0x4802 2000 0x4802 2FFF 4KB Peripheral Registers

0x4802 3000 0x4802 3FFF 4KB Support Registers

UART2 0x4802 4000 0x4802 4FFF 4KB Peripheral Registers

0x4802 5000 0x4802 5FFF 4KB Support Registers

Reserved 0x4802 6000 0x4802 7FFF 8KB Reserved

I2C0 0x4802 8000 0x4802 8FFF 4KB Peripheral Registers

0x4802 9000 0x4802 9FFF 4KB Support Registers

I2C1 0x4802 A000 0x4802 AFFF 4KB Peripheral Registers

0x4802 B000 0x4802 BFFF 4KB Support Registers

Reserved 0x4802 C000 0x4802 DFFF 8KB Reserved

TIMER1 0x4802 E000 0x4802 EFFF 4KB Peripheral Registers

0x4802 F000 0x4802 FFFF 4KB Support Registers

SPIOCP 0x4803 0000 0x4803 0FFF 4KB Peripheral Registers

0x4803 1000 0x4803 1FFF 4KB Support Registers

GPIO0 0x4803 2000 0x4803 2FFF 4KB Peripheral Registers

0x4803 3000 0x4803 3FFF 4KB Support Registers

Reserved 0x4803 4000 0x4803 7FFF 16KB Reserved

McASP0 CFG 0x4803 8000 0x4803 9FFF 8KB Peripheral Registers

0x4803 A000 0x4803 AFFF 4KB Support Registers

Reserved 0x4803 B000 0x4803 BFFF 4KB Reserved

McASP1 CFG 0x4803 C000 0x4803 DFFF 8KB Peripheral Registers

0x4803 E000 0x4803 EFFF 4KB Support Registers

Reserved 0x4803 F000 0x4803 FFFF 4KB Reserved

TIMER2 0x4804 0000 0x4804 0FFF 4KB Peripheral Registers

0x4804 1000 0x4804 1FFF 4KB Support Registers

TIMER3 0x4804 2000 0x4804 2FFF 4KB Peripheral Registers

0x4804 3000 0x4804 3FFF 4KB Support Registers

TIMER4 0x4804 4000 0x4804 4FFF 4KB Peripheral Registers

0x4804 5000 0x4804 5FFF 4KB Support Registers

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Table 2-17. L4 Standard Peripheral Memory Map (continued)

START ADDRESS

DEVICE NAME END ADDRESS (HEX) SIZE DESCRIPTION

(HEX)

TIMER5 0x4804 6000 0x4804 6FFF 4KB Peripheral Registers

0x4804 7000 0x4804 7FFF 4KB Support Registers

TIMER6 0x4804 8000 0x4804 8FFF 4KB Peripheral Registers

0x4804 9000 0x4804 9FFF 4KB Support Registers

TIMER7 0x4804 A000 0x4804 AFFF 4KB Peripheral Registers

0x4804 B000 0x4804 BFFF 4KB Support Registers

GPIO1 0x4804 C000 0x4804 CFFF 4KB Peripheral Registers

0x4804 D000 0x4804 DFFF 4KB Support Registers

Reserved 0x4804 E000 0x4804 FFFF 8KB Reserved

McASP2 CFG 0x4805 0000 0x4805 1FFF 8KB Peripheral Registers

0x4805 2000 0x4805 2FFF 4KB Support Registers

Reserved 0x4805 3000 0x4805 FFFF 52KB Reserved

SD/SDIO 0x4806 0000 0x4806 FFFF 64KB Registers

0x4807 0000 0x4807 0FFF 4KB Support Registers

Reserved 0x4807 1000 0x4807 FFFF 60KB Reserved

ELM 0x4808 0000 0x4808 FFFF 64KB Error Location Module

0x4809 0000 0x4809 0FFF 4KB Support Registers

Reserved 0x4809 1000 0x480B FFFF 188KB Reserved

RTC 0x480C 0000 0x480C 0FFF 4KB Peripheral Registers

0x480C 1000 0x480C 1FFF 4KB Support Registers

WDT1 0x480C 2000 0x480C 2FFF 4KB Peripheral Registers

0x480C 3000 0x480C 3FFF 4KB Support Registers

Reserved 0x480C 4000 0x480C 7FFF 16KB Reserved

Mailbox 0x480C 8000 0x480C 8FFF 4KB Peripheral Registers

0x480C 9000 0x480C 9FFF 4KB Support Registers

Spinlock 0x480C A000 0x480C AFFF 4KB Peripheral Registers

0x480C B000 0x480C BFFF 4KB Support Registers

Reserved 0x480C C000 0x480F FFFF 208KB Reserved

HDVPSS 0x4810 0000 0x4811 FFFF 128KB Peripheral Registers

0x4812 0000 0x4812 0FFF 4KB Support Registers

Reserved 0x4812 1000 0x4812 1FFF 4KB Reserved

HDMI 1.3 Tx 0x4812 2000 0x4812 2FFF 4KB Peripheral Registers

0x4812 3000 0x4812 3FFF 4KB Support Registers

Reserved 0x4812 4000 0x4813 FFFF 112KB Reserved

Control Module 0x4814 0000 0x4815 FFFF 128KB Peripheral Registers

0x4816 0000 0x4816 0FFF 4KB Support Registers

Reserved 0x4816 1000 0x4817 FFFF 124KB Reserved

PRCM 0x4818 0000 0x4818 2FFF 12KB Peripheral Registers

0x4818 3000 0x4818 3FFF 4KB Support Registers

Reserved 0x4818 4000 0x4818 7FFF 16KB Reserved

SmartReflex0 0x4818 8000 0x4818 8FFF 4KB Peripheral Registers

0x4818 9000 0x4818 9FFF 4KB Support Registers

SmartReflex1 0x4818 A000 0x4818 AFFF 4KB Peripheral Registers

0x4818 B000 0x4818 BFFF 4KB Support Registers

OCP Watchpoint 0x4818 C000 0x4818 CFFF 4KB Peripheral Registers

0x4818 D000 0x4818 DFFF 4KB Support Registers

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