Marvell 88E1510/12/14/18系列10/100/1000Mbps节能以太网收发器数据手册

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Marvell的88E1512芯片手册是一份详细介绍Marvell Alaska系列的集成10/100/1000Mbps能源效率以太网收发器的官方技术文档。这份文档编号为MV-S107146-U0,修订版B，发布日期为2018年2月23日，其分类为公开，可供公众查阅。 88E1510/88E1518/88E1512/88E1514芯片是该系列的核心产品，它们专为满足高效能、低功耗的网络通信需求而设计。它们支持多种速率的以太网标准，包括10Mbps、100Mbps和1000Mbps（Gigabit Ethernet），适用于各种现代网络基础设施，如路由器、交换机和物联网设备。文档中提供了详细的技术规格、功能特性、电气特性以及操作和安装指南，确保用户能够正确理解和配置这些芯片。值得注意的是，手册中包含了一些重要的警告和提示，如可能对硬件或软件造成损害的信息，个人伤害的风险，以及在使用过程中需遵循的安全措施。此外，文档还包含了免责声明，强调未经Marvell明确书面许可，不得以任何形式复制或传输文档内容。Marvell保留随时修改文档的权利，且不承担因文档信息而产生的任何责任，包括但不限于产品的适销性或特定用途的适用性。同时，Marvell并不保证文档中的信息的准确性或完整性。为了获取更多关于88E1512芯片的最新信息和技术支持，用户应访问Marvell的官方网站<http://www.marvell.com>。这本手册对于系统设计师、工程师以及网络管理员来说，是一份不可或缺的参考资料，帮助他们在实际应用中实现高效能、低成本的网络连接。

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 16 Document Classification: Public February 23, 2018

Figure 34: MDC/MDIO Timing ........................................................................................................................138

Figure 35: ........................................................................................................................................................139

Figure 36: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing ........................................................140

Figure 37: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................141

Figure 38: 10/100/1000BASE-T to SGMII Latency Timing ..............................................................................142

Figure 39: SGMII to 10/100/1000BASE-T Latency Timing ..............................................................................142

5 Package Mechanical Dimensions .................................................................................................143

Figure 40: 88E1510/88E1518 48-pin QFN Package Mechanical Drawings ....................................................143

Figure 41: 88E1512/88E1514 56-pin QFN Package Mechanical Drawings ....................................................145

6 Part Order Numbering/Package Marking......................................................................................147

Figure 42: Sample Part Number ......................................................................................................................147

Figure 43: 88E1510 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................149

Figure 44: 88E1518 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 45: 88E1512 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 46: 88E1514 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................151

Figure 47: 88E1510 48-pin QFN Industrial Package Marking and Pin 1 Location...........................................151

Figure 48: 88E1512 56-pin QFN Industrial Package Marking and Pin 1 Location...........................................152

A Revision History .............................................................................................................................153

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 20 Document Classification: Public February 23, 2018

The RGMII supports 10/100/1000BASE-T modes of operation.

Table 4: RGMII

48-QFN

Pin #

Pin Name Pin

Type

Description

47 TX_CLK I RGMII Transmit Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance depending on speed.

2 TX_CTRL I RGMII Transmit Control. TX_EN is presented on the rising edge of TX_CLK.

A logical derivative of TX_EN and TX_ER is presented on the falling edge of

TX_CLK.

TXD[3]

TXD[2]

TXD[1]

TXD[0]

I RGMII Transmit Data.

TXD[3:0] run at double data rate with bits [3:0] of each byte to be transmitted

on the rising edge of TX_CLK, and bits [7:4] presented on the falling edge of

TX_CLK.

In 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on

the rising edge of TX_CLK.

40 RX_CLK O RGMII Receive Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance derived from the received data stream

depending on speed.

37 RX_CTRL O RGMII Receive Control. RX_DV is presented on the rising edge of RX_CLK.

A logical derivative of RX_DV and RX_ER is presented on the falling edge of

RX_CLK.

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O RGMII Receive Data. RXD[3:0] run at double data rate with bits [3:0] of each

byte received on the rising edge of RX_CLK, and bits [7:4] presented on the

falling edge of RX_CLK.

In 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on

the rising edge of RX_CLK.

Table 5: Management Interface and Interrupt

48-QFN

Pin #

Pin Name Pin

Type

Description

4 MDC I MDC is the management data clock reference for the serial management

interface. A continuous clock stream is not expected. The maximum frequency

supported is 12 MHz.

5 MDIO I/O MDIO is the management data. MDIO transfers management data in and out of

the device synchronously to MDC. This pin requires a pull-up resistor in a

range from 1.5 kΩ to 10 kΩ.

Table 6: LED Interface

48-QFN

Pin #

Pin Name Pin

Type

Description

10 LED[0] O LED output.

9 LED[1] I/O LED output

8 LED[2]/INTn O LED/Interrupt outputs.

LED[2] pin also functions as an active low interrupt pin.

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