TI MSP430F2619：超低功耗16位微控制器技术规格

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"MSP430F2619是德州仪器(TI)推出的一款混合信号微控制器，适用于需要低功耗和高性能的嵌入式应用。该微控制器具有广泛的电源电压范围（1.8V至3.6V），在不同工作模式下表现出极低的功率消耗，如在1MHz、2.2V时主动模式下的电流仅为365μA，而待机模式（VLO）下则低至0.5μA，内存保留的关闭模式仅消耗0.1μA。" MSP430F2619微控制器的主要特点包括： 1. **快速唤醒功能**：从待机模式唤醒到工作状态能在1微秒内完成，这对于实时响应要求高的应用非常有利。 2. **16位RISC架构**：采用高效的16位RISC指令集，执行速度高达62.5纳秒的指令周期时间，保证了高计算性能。 3. **内部直接存储器访问(DMA)**：提供3个通道的内部DMA，支持数据传输，减轻CPU负担，提高系统效率。 4. **12位模数转换器(A/D)**：内置12位A/D转换器，带有内部参考源、采样保持功能和自动扫描特性，适合进行精确的模拟信号数字化。 5. **双12位数模转换器(D/A)**：两个12位D/A转换器可以同步工作，为模拟信号输出提供高精度。 6. **丰富的定时器和比较器**：包括16位Timer_A和Timer_B，分别带有3个和7个捕获/比较寄存器，可实现多种定时和计数任务。 7. **多用途串行通信接口(USCIs)**：提供4个USCI接口，支持增强型UART（自动波特率检测）、IrDA编码解码器、同步SPI以及I2C通信协议。 8. **电源电压监控**：集成了电源电压监控器，具有可编程电压检测级别，可以确保系统稳定运行。 9. **棕色出检测器**：在电源电压下降到危险水平时，触发保护机制，防止系统损坏。 MSP430F2619微控制器因其超低功耗和丰富的外设接口，广泛应用于能源管理、传感器接口、医疗设备、工业自动化以及消费电子等领域。这款芯片的设计理念是为了在有限的电源预算下，提供强大的处理能力和灵活的通信选项，使得开发者能够在设计中平衡性能与功耗，以满足多样化的应用需求。

MSP430F241x, MSP430F261x

MIXED SIGNAL MICROCONTROLLER

SLAS541D -- JUNE 2007 -- REVISED NOVEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

special function registers

Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated

to a functional purpose are not physically present in the device. This arrangement provides simple software

access.

interrupt enable 1 and 2

Address76543210

00h

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw--0

Interrupt Enable Register 1

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected.

Active if watchdog timer is configured as general-purpose timer.

OFIE Oscillator fault interrupt enable

NMIIE Nonmaskable interrupt enable

ACCVIE Flash memory access violation interrupt enable

Address76543210

01h

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw--0 rw--0 rw--0 rw--0

Interrupt Enable Register 2

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

MSP430F241x, MSP430F261x

MIXED SIGNAL MICROCONTROLLER

SLAS541D -- JUNE 2007 -- REVISED NOVEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

memory organization

MSP430F2416

MSP430F2616

MSP430F2417

MSP430F2617

Memory

Main: interrupt vector

Main: code memory

Size

Flash

92KB

0x0FFFF -- 0x0FFC0

0x18FFF -- 0x02100

92KB

0x0FFFF -- 0x0FFC0

0x19FFF -- 0x03100

RAM (total)

Extended

Mirrored

Size

4kB

0x020FF -- 0x01100

2kB

0x020FF -- 0x01900

2kB

0x018FF -- 0x01100

8kB

0x030FF -- 0x01100

6kB

0x030FF -- 0x01900

2kB

0x018FF -- 0x01100

Information memory Size

Flash

256 Byte

0x010FF -- 0x01000

256 Byte

0x010FF -- 0x01000

Boot memory Size

ROM

1KB

0x00FFF -- 0x00C00

1KB

0x00FFF -- 0x00C00

RAM (mirrored at

0x18FF to 0x01100)

Size 2KB

0x009FF -- 0x00200

2KB

0x009FF -- 0x00200

Peripherals 16-bit

8-bit

8-bit SFR

0x001FF -- 0x00100

0x000FF -- 0x00010

0x0000F -- 0x00000

0x001FF -- 0x00100

0x000FF -- 0x00010

0x0000F -- 0x00000

MSP430F2618

MSP430F2418

MSP430F2619

MSP430F2419

Memory

Main: interrupt vector

Main: code memory

Size

Flash

116KB

0x0FFFF -- 0x0FFC0

0x1FFFF -- 0x03100

120KB

0x0FFFF -- 0x0FFC0

0x1FFFF -- 0x02100

RAM (total)

Extended

Mirrored

Size

8kB

0x030FF -- 0x01100

6kB

0x030FF -- 0x01900

2kB

0x018FF -- 0x01100

4kB

0x020FF -- 0x01100

2kB

0x020FF -- 0x01900

2kB

0x018FF -- 0x01100

Information memory Size

Flash

256 Byte

0x010FF -- 0x01000

256 Byte

0x010FF -- 0x01000

Boot memory Size

ROM

1KB

0x00FFF -- 0x00C00

1KB

0x00FFF -- 0x00C00

RAM (mirrored at

0x18FF to 0x01100)

Size 2KB

0x009FF -- 0x00200

2KB

0x009FF -- 0x00200

Peripherals 16-bit

8-bit

8-bit SFR

0x001FF -- 0x00100

0x000FF -- 0x00010

0x0000F -- 0x00000

0x001FF -- 0x00100

0x000FF -- 0x00010

0x0000F -- 0x00000

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access

to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the

features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap

Loader, literature number SLAA089.

BSL Function PM, PN Package Pins ZQW Package Pins

Data Transmit 13 -- P1.1 H1 - P1.1

Data Receive 22 -- P2.2 M3 - P2.2

MSP430F241x, MSP430F261x

MIXED SIGNAL MICROCONTROLLER

SLAS541D -- JUNE 2007 -- REVISED NOVEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.

It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.

D Flash content integrity check with marginal read modes

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number

SLAU144.

DMA controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using

the DMA controller c an increase the throughput of peripheral modules. The DMA controller reduces system

power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to

or from a peripheral.

oscillator and system clock

The clock system in the MSP430x241x and MSP43x261x family of devices is supported by the basic clock

module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low-frequency

oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock

module is designed to meet the requirements of both low system cost and low power consumption. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the

following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very

low-power LF oscillator

D Main clock (MCLK), the system clock used by the CPU

D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

MSP430F241x, MSP430F261x

MIXED SIGNAL MICROCONTROLLER

SLAS541D -- JUNE 2007 -- REVISED NOVEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

calibration data stored in information memory segment A

Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.

TAGS USED BY THE ADC CALIBRATION TAGS

NAME ADDRESS VALUE DESCRIPTION

TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and T

=25°C at calibration

TAG_ADC12_1 0x10DA 0x10 ADC12_1 calibration tag

TAG_EMPTY -- 0xFE Identifier for empty memory areas

LABELS USED BY THE ADC CALIBRATION TAGS

LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE ADDRESS OFFSET

CAL_ADC_25T85 INCHx = 0x1010; REF2_5 = 1, T

=85°C word 0x000E

CAL_ADC_25T30 INCHx = 0x1010; REF2_5 = 1, T

=30°C word 0x000C

CAL_ADC_25VREF_FACTOR REF2_5 = 1, T

=30°C word 0x000A

CAL_ADC_15T85 INCHx = 0x1010; REF2_5 = 0, T

=85°C word 0x0008

CAL_ADC_15T30 INCHx = 0x1010; REF2_5 = 0, T

=30°C word 0x0006

CAL_ADC_15VREF_FACTOR REF2_5 = 0, T

=30°C word 0x0004

CAL_ADC_OFFSET External V

REF

=1.5V,f

ADC12CLK

=5MHz word 0x0002

CAL_ADC_GAIN_FACTOR External V

REF

=1.5V,f

ADC12CLK

=5MHz word 0x0000

CAL_BC1_1MHZ -- byte 0x0007

CAL_DCO_1MHZ -- byte 0x0006

CAL_BC1_8MHZ -- byte 0x0005

CAL_DCO_8MHZ -- byte 0x0004

CAL_BC1_12MHZ -- byte 0x0003

CAL_DCO_12MHZ -- byte 0x0002

CAL_BC1_16MHZ -- byte 0x0001

CAL_DCO_16MHZ -- byte 0x0000

brownout, supply voltage supervisor (SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports

both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the

device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V

may not

have ramped to V

CC(min)

at that time. The user must ensure that the default DCO settings are not changed until

reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when V

reaches V

CC(min)

digital I/O

There are up to eight 8-bit I/O ports implemented—ports P1 through P8:

D All individual I/O bits are independently programmable.

D Any combination of input, output, and interrupt conditions is possible.

D Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.

D Read/write access to port-control registers is supported by all instructions.

D Each I/O has an individually programmable pullup/pulldown resistor.

D Ports P7/P8 can be accessed word-wise.

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