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The JESD209-4C: 2020 Low Power Double Data Rate 4 (LPDDR4) standard is a comprehensive guide to the latest advancements in memory technology. This revision of the previous JESD209-4B version from February 2017 provides a detailed overview of LPDDR4 specifications and requirements. The document, totaling 355 pages, covers a wide range of topics related to LPDDR4 technology. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, the organization responsible for developing this standard, ensures that all content in the document has been thoroughly reviewed and approved by industry experts. The purpose of these standards is to promote clarity and consistency in the manufacturing and use of LPDDR4 devices. LPDDR4 is renowned for its low power consumption and high data transfer speeds, making it a popular choice for mobile devices and other memory-intensive applications. The JESD209-4C standard outlines the technical specifications, electrical characteristics, timing parameters, and signal definitions required for LPDDR4 devices to function optimally. By adhering to the guidelines set forth in the JESD209-4C standard, manufacturers can produce LPDDR4 memory modules that are compatible with a wide range of devices and systems. This ensures interoperability and reliability, enhancing the overall user experience and performance of electronic devices. Overall, the JESD209-4C standard is an essential resource for anyone involved in the design, production, or use of LPDDR4 memory technology. It provides a comprehensive and detailed overview of the latest advancements in memory technology, setting the standard for high-performance, low-power memory solutions in the industry.

JEDEC Standard No. 209-4C

xiv

800MHz, ODT Worst Timing Case .....................................................................................115

Figure 51 — Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble ............................................116

Figure 52 — Consecutive Writes Operation: tCCD = Min + 1, 0.5nCK Postamble ..................................117

Figure 53 — Consecutive Writes Operation: tCCD = Min + 1, 1.5nCK Postamble ..................................118

Figure 54 — Consecutive Writes Operation: tCCD = Min + 2, 0.5nCK Postamble ..................................119

Figure 55 — Consecutive Writes Operation: tCCD = Min + 2, 1.5nCK Postamble ..................................120

Figure 56 — Consecutive Writes Operation: tCCD = Min + 3, 0.5nCK Postamble ..................................121

Figure 57 — Consecutive Writes Operation: tCCD = Min + 3, 1.5nCK Postamble ..................................122

Figure 58 — Consecutive Writes Operation: tCCD = Min + 4, 1.5nCK Postamble ..................................123

Figure 59 — Masked Write Command - Same Bank ...............................................................................125

Figure 60 — Masked Write Command - Different Bank ...........................................................................126

Figure 61 — Masked Write Command w/ Write DBI Enabled; DM Enabled ............................................131

Figure 62 — Write Command w/ Write DBI Enabled; DM Disabled .........................................................132

Figure 63 — Burst READ followed by PRECHARGE

(Shown with BL16, 2tCK pre-amble)...................................................................................134

Figure 64 — Burst READ followed by PRECHARGE

(Shown with BL32, 2tCK pre-amble)...................................................................................134

Figure 65 — Burst WRITE Followed by PRECHARGE

(Shown with BL16, 2tCK pre-amble)...................................................................................135

Figure 66 — Burst READ with Auto-Precharge

(Shown with BL16, 2tCK pre-amble)...................................................................................136

Figure 67 — Burst READ with Auto-Precharge

(Shown with BL32, 2tCK pre-amble)...................................................................................136

Figure 68 — Burst WRITE with Auto-Precharge

(Shown with BL16, 2tCK pre-amble)...................................................................................137

Figure 69 — Command Input Timing with RAS lock ................................................................................138

Figure 70 — Delay time from Write to Read with Auto-Precharge ...........................................................139

Figure 71 — All Bank Refresh Operation .................................................................................................148

Figure 72 — Per Bank Refresh to a different bank Operation..................................................................148

Figure 73 — Per Bank Refresh to the same bank Operation ...................................................................149

Figure 74 — Pulling-in Refresh Commands (Example)............................................................................151

Figure 75 — Burst Read operation followed by Per Bank Refresh ..........................................................152

Figure 76 — Burst Read with Auto-Precharge operation followed by Per Bank Refresh.........................152

Figure 77 — Self Refresh Entry and Exit..................................................................................................154

Figure 78 — Self Refresh Entry/Exit Timing.............................................................................................155

Figure 79 — Self Refresh Entry/Exit Timing with Power Down Entry/Exit................................................155

Figure 80 — Command input timings after Power Down Exit during Self Refresh...................................157

Figure 81 — tESCKE Timing....................................................................................................................158

Figure 82 — MRR, MRW and MPC Commands Issuing Timing during tXSR..........................................159

Figure 83 — MRR, MRW and MPC Commands Issuing Timing during tRFC..........................................159

Figure 84 — Mode Register Read Operation ...........................................................................................161

Figure 85 — READ to MRR Timing..........................................................................................................162

Figure 86 — Write to MRR Timing ...........................................................................................................163

Figure 87 — MRR Following Power-Down...............................................................................................163

Figure 88 — Mode Register Write Timing ................................................................................................165

Figure 89 — VRCG Enable timing............................................................................................................168

Figure 90 — VRCG Disable timing...........................................................................................................168

Figure 91 — VREF operating range (VREFmin, VREFmax) ....................................................................169

Figure 92 — Example of VREF set tolerance (max case only shown) and step size...............................170

Figure 93 — VREF_time for Short, Middle and Long Timing Diagram.....................................................171

Figure 94 — VREF step single step size increment case ........................................................................172

Figure 95 — VREF step single step size decrement case .......................................................................172

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JEDEC Standard No. 209-4C

Figure 96 — VREF full step from VREFmin to VREFmax case ...............................................................173

Figure 97 — VREF full step from VREFmax to VREFmin case ...............................................................173

Figure 98 — VREF operating range(VREFmin, VREFmax).....................................................................175

Figure 99 — Example of VREF set tolerance (max case only shown) and step size...............................176

Figure 100 — VREF_time for Short, Middle and Long Timing Diagram...................................................177

Figure 101 — VREF step single step size increment case ......................................................................178

Figure 102 — VREF step single step size decrement case .....................................................................178

Figure 103 — VREF full step from VREFmin to VREFmax case .............................................................179

Figure 104 — VREF full step from VREFmax to VREFmin case .............................................................179

Figure 105 — Entering Command Bus Training Mode and CA Training Pattern Input and Output with VREF-

CA Value Update ................................................................................................................184

Figure 106 — Consecutive VREFCA Value Update.................................................................................185

Figure 107 — Exiting Command Bus Training Mode with Valid Command .............................................186

Figure 108 — Exiting Command Bus Training Mode with Power Down Entry .........................................187

Figure 109 — Entering Command Bus Training Mode and CA Training Pattern Input and Output .........193

Figure 110 — Exiting Command Bus Training Mode with Valid Command .............................................194

Figure 111 — Exiting Command Bus Training Mode with Power Down Entry .........................................195

Figure 112 — Entering Command Bus Training Mode and CA Training Pattern Input with VrefCA Value Up-

date .....................................................................................................................................200

Figure 113 — CA pattern Input/Output to Vref setting Input.....................................................................201

Figure 114 — Consecutive CA training pattern Input/Output ...................................................................202

Figure 115 — Exiting Command Bus Training Mode ...............................................................................203

Figure 116 — DQS ODT Timing during Command Bus Training Mode 2................................................204

Figure 117 — Frequency Set Point Switching Timing ..............................................................................209

Figure 118 — Training Two Frequency Set-Points ..................................................................................211

Figure 119 — Switching Between Two Trained Frequency Set-Points....................................................211

Figure 120 — Switching to a Third Trained Frequency Set-Point ............................................................212

Figure 121 — Write Leveling Timing, tDQSL(max) ..................................................................................214

Figure 122 — Write Leveling Timing, tDQSL(min) ...................................................................................214

Figure 123 — Clock Stop and Timing during Write Leveling....................................................................215

Figure 124 — DQS_t/DQS_c to CK_t/CK_c timings at the DRAM pins referenced from the internal latch ...

216

Figure 125 — DQ Read Training Timing: Read to Read DQ Calibration .................................................218

Figure 126 — DQ Read Training Timing: Read DQ Cal. to Read DQ Cal. / Read...................................219

Figure 127 — MPC Read DQ Calibration Following Power-Down State .................................................221

Figure 128 — Write to MPC [Write FIFO] Operation Timing ....................................................................226

Figure 129 — MPC [Write FIFO] to MPC [Read FIFO] Timing.................................................................227

Figure 130 — MPC [Read FIFO] to Read Timing.....................................................................................228

Figure 131 — MPC [Write FIFO] with DQ ODT Timing ............................................................................229

Figure 132 — Power Down Exit to MPC [Write FIFO] Timing ..................................................................230

Figure 133 — Interval oscillator offset OSCoffset ....................................................................................233

Figure 134 — In case of DQS Interval Oscillator is stopped by MPC Command.....................................235

Figure 135 — In case of DQS Interval Oscillator is stopped by DQS interval timer .................................235

Figure 136 — Read Preamble Training....................................................................................................237

Figure 137 — MPC [WRITE FIFO] Operation : tWPRE=2nCK, tWPST=0.5nCK.....................................240

Figure 138 — MPC [RD FIFO] Read Operation :

tWPRE=2nCK, tWPST=0.5nCK, tRPRE=toggling, tRPST=1.5nCK ...................................240

Figure 139 — MPC [RD FIFO] Operation : tRPRE=toggling, tRPST=1.5nCK .........................................241

Figure 140 — Temp Sensor Timing .........................................................................................................245

Figure 141 — ZQCal Timing.....................................................................................................................246

Figure 142 — Functional Representation of CA ODT ..............................................................................249

Figure 143 — On Die Termination for CA ................................................................................................250

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JEDEC Standard No. 209-4C

xvi

Figure 144 — ODT for Command/Address setting update timing in 4 Clock Cycle Command................253

Figure 145 — Functional Representation of ODT ....................................................................................254

Figure 146 — Asynchronous ODTon/ODToff Timing ...............................................................................256

Figure 147 — On Die Termination............................................................................................................257

Figure 148 — Basic Power-Down Entry and Exit Timing .........................................................................262

Figure 149 — Read and Read with Auto-Precharge to Power-Down Entry .............................................262

Figure 150 — Write and Mask Write to Power-Down Entry .....................................................................263

Figure 151 — Write with Auto-Precharge and Mask Write with Auto-Precharge to Power-Down Entry ..263

Figure 152 — Refresh entry to Power-Down Entry ..................................................................................264

Figure 153 — Activate Command to Power-Down Entry .........................................................................264

Figure 154 — Precharge Command to Power-Down Entry......................................................................265

Figure 155 — Mode Register Read to Power-Down Entry.......................................................................265

Figure 156 — Mode Register Write to Power-Down Entry .......................................................................266

Figure 157 — Multi-Purpose Command for Start ZQ Calibration to Power-Down Entry ..........................266

Figure 158 — tCMDCKE Timing ..............................................................................................................267

Figure 159 — TRR Mode .........................................................................................................................274

Figure 160 — PPR Timing........................................................................................................................276

Figure 161 — LPDDR4 Input AC timing definition for CKE ......................................................................279

Figure 162 — LPDDR4 Input AC timing definition for Reset_n and ODT_CA .........................................279

Figure 163 — AC Overshoot and Undershoot Definition for Address and Control Pins...........................280

Figure 164 — CK Differential Input Voltage .............................................................................................281

Figure 165 — Definition of differential Clock Peak Voltage......................................................................282

Figure 166 — Clock Single-Ended Input Voltage .....................................................................................283

Figure 167 — Differential Input Slew Rate Definition for CK_t, CK_c ......................................................284

Figure 168 — Vix Definition (Clock) .........................................................................................................285

Figure 169 — DQS Differential Input Voltage...........................................................................................286

Figure 170 — Definition of differential DQS Peak Voltage .......................................................................287

Figure 171 — DQS Single-Ended Input Voltage ......................................................................................288

Figure 172 — Differential Input Slew Rate Definition for DQS_t, DQS_c.................................................289

Figure 173 — Vix Definition (DQS)...........................................................................................................290

Figure 174 — Single Ended Output Slew Rate Definition ........................................................................291

Figure 175 — Differential Output Slew Rate Definition ............................................................................292

Figure 176 — Overshoot and Undershoot Definition................................................................................293

Figure 177 — Driver Output Reference Load for Timing and Slew Rate .................................................294

Figure 178 — LVSTL I/O Cell...................................................................................................................295

Figure 179 — Pull-down calibration..........................................................................................................295

Figure 180 — Pull-up calibration ..............................................................................................................296

Figure 181 — CA Receiver (Rx) mask .....................................................................................................321

Figure 182 — Across pin VREFCA voltage variation ...............................................................................321

Figure 183 — CA Timings at the DRAM Pins...........................................................................................322

Figure 184 — CA TcIPW and SRIN_cIVW definition (for each input pulse).............................................322

Figure 185 — CA VIHL_AC definition (for each input pulse)....................................................................323

Figure 186 — Read data timing definitions tQH and tDQSQ across all DQ signals per DQS group .......324

Figure 187 — Read data timing tQW valid window defined per DQ signal ..............................................325

Figure 188 — DQ Receiver(Rx) mask......................................................................................................328

Figure 189 — Across pin Vref DQ voltage variation.................................................................................328

Figure 190 — DQ to DQS tDQS2DQ and tDQ2DQ Timings at the DRAM pins

referenced from the internal latch .......................................................................................329

Figure 191 — DQ TdIPW and SRIN_dIVW definition (for each input pulse)............................................330

Figure 192 — DQ VIHL_AC definition (for each input pulse) ...................................................................330

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