CH7036 RGB/HDMI/LVDS 编码器数据手册

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"CH7036是一款视频信号转换芯片，能将LVDS信号转换为HDMI或VGA信号，同时保留LVDS信号的BYPASS功能。该芯片支持的输入LVDS信号最高分辨率为1366X768，并且提供完整的功能集。" CH7036是一款由Chrontel公司生产的高性能RGB/HDMI/LVDS编码器，适用于多种显示设备的信号转换。以下是其主要特性和功能的详细说明： 1. **单通道18位/24位LVDS接收器和发射器**：CH7036能够接收和发送LVDS信号，最高支持到1366x768的分辨率，满足高清显示需求。 2. **HDMI编码器**：内置的HDMI编码器可支持高达1080p的高清视频输出，适应高清晰度电视和显示器的需求。 3. **VGA显示支持**：除了HDMI，CH7036也支持VGA接口，同样能提供1080p的分辨率，确保在没有HDMI接口的设备上也能正常工作。 4. **HDMI重播功能**：芯片具备HDMI重播功能，可用于信号中继，延长HDMI信号传输距离。 5. **DDC主控及EDID读取**：支持Display Data Channel (DDC) 主控，用于读取显示器的Extended Display Identification Data (EDID)，确保与显示器的兼容性。 6. **热插拔检测（HPD）**：集成对HDMI/DVI的热插拔检测，能在设备插入或拔出时自动调整状态。 7. **可选HDCP 1.1**：如果需要，可以启用High-bandwidth Digital Content Protection (HDCP) 1.1，保护数字内容不被非法复制。 8. **10位高速DAC**：包含三个10位高速数模转换器，用于高质量的模拟信号输出。 9. **DAC开关控制**：通过编程内部寄存器可以关闭DAC，以适应不同应用场景。 10. **复合同步信号支持**：支持独立的复合同步信号，增强系统兼容性。 11. **监控连接检测**：具备检测显示器连接状态的能力，连接状态可通过内部寄存器查询。 12. **像素级色彩增强**：对于模拟RGB输入，提供亮度和对比度的像素级增强。 13. **SPDIF音频接口**：支持最高20位数据流、192kHz/2声道的SPDIF音频接口，实现高品质音频输出。 14. **I2S数字音频输入**：兼容多种采样率的I2S数字音频输入，最高可达24位数据流，包括常见的音乐采样率。 15. **片上帧缓冲**：内置的帧缓冲允许灵活的输入LVDS视频定时，使信号转换更加稳定和流畅。 16. **视频帧率转换**：能够转换输入视频帧率，适应不同源和目标设备的帧率需求。 CH7036是一款功能全面的视频信号转换芯片，广泛应用于需要LVDS、HDMI或VGA信号转换的场合，如显示器、投影仪、电视盒等设备。其强大的信号处理能力和丰富的功能选项，使得它在各种显示应用中具有很高的实用价值。

CHRONTEL

CH7036

201-1000-009 Rev. 1.24, 08/15/2011 11

The CH7036 supports 32k/2ch, 44.1kHz/2ch, 48kHz/2ch, 88.2kHz/2ch, 96kHz/2ch, 176.4kHz/2ch and 192kHz/2ch

SPDIF input, and the maximum signal data width is up to 20 bits (Refer to Figure 5 for SPDIF interface format).

To select the S/PDIF audio input format, the bit-6 of the offset 1Eh - Register Page 1 needs to set to “1”; the bit-0 of

the offset 07h - Register Page 1 will also need to be switched to “0” to power on the decoder. The CH7036 audio

decoder is cable of detecting incoming S/PIDF frequency and dynamically sampling the audio stream.

Frame 191 Frame 0 Frame 1 Frame 191 Frame 0

W B W M

Preamble Auxiliary LSB MSB U V C P

0 3 4 7 8 11 12 27 28 31

16-bit of bitstream

1 block = 192 Frame

Figure 5: SPDIF interface format

2.2.2 I2S Input

The I

S Bus (Inter-IC Sound [I2S]) is another digital audio format supported by CH7036. This serial bus audio

interface consists of three serial bus lines: a line with data channel [SD], a word select line [WS], and a clock line

[SCK]. Data is transmitted in two's complement, MSB first.

The built-in I

S decoder supports the following encode formats

1. Left-justified I2S mode, 16bits/20bits/24bit

2. Right-justified I2S mode, 16bits/20bits/24bit

3. Standard I2S mode, 16bits/20bits/24bit

The CH7036’s Pin 51, Pin 52 and Pin 53 are dedicated for the I

S connection. The I

S decoder can be enabled by

setting “0” to the bit-6 of the offset 1Eh - Register Page 1. In addition, the bit-6 of the Register 07h - Register Page

1 will also need to be switched to “0” to power on the decoder.

MSB LSB MSB LSB MSB

Channel A Channel B

OLRCK

OSCLK

SDOUT

Left

Justified

(Out)

OLRCK

OSCLK

SDOUT

(Out)

MSB LSB MSB LSB MSB

Channel A Channel B

MSB LSB MSB LSB

Channel A Channel B

OLRCK

OSCLK

SDOUT

Right

Justified

(Out)

MSB Extended MSB Extended

Figure 6: I2S interface format

CHRONTEL

CH7036

12 201-1000-009 Rev. 1. 24, 08/15/2011

2.3 DAC Output

2.3.1 Analog RGB Output

The CH7036 has three high speed video DACs for supporting analog RGB outputs. Two additional pins also

provide vertical sync and horizontal sync for driving the analog RGB monitor. A composite sync is available

through programming registers (Table 3). The CH7036 can support analog RGB display resolution up to 1080p.

Table 3: Composite sync type

CSSEL[2:0] Composite sync type

0 Vsync XOR Hsync

1 Vsync OR Hsync

2 Vsync AND Hsync

3 Vsync XOR Hsync 2

4 Vsync XOR Hsync 3

5 Vsync XOR Hsync +

Equalizing pluse 1

6 Vsync XOR Hsync +

Equalizing pluse 2

7 (~Vsync) AND Hsync OR

Vsync

2.3.2 DAC output Configuration

Analog RGB components output can be reassigned to any of the three DACs output pins of the CH7036 through

registers programming. Table 4 below lists the DAC output mappings:

Table 4: Video DAC Configurations for The chip

DACSP[2:0] DAC0 DAC1 DAC2

000 R G B

001 R B G

010 G R B

011 G B R

100 B R G

101 B G R

Each DAC can output R or G or B based on the setting of DACSP[2:0] in the offset 75h[2:0] – Register Page 1;

default value is “000”  DAC0=R, DAC1=G, DAC2=B.

2.3.3 DAC single/double termination

The CH7036’s DAC output can be single terminated (75 Ω) or double terminated (37.5 Ω). Using the single

termination will reduce device’s power consumption while the double termination can improve the performance and

stability. Please refer to the description of the SEL_R bit, which is the bit-5 of the offset 1Ah - Register Page 2.

2.3.4 DAC connection detect

The chip will automatically detect the DAC connection status in every 1 second interval in default mode. To read

back the status of the DAC connection, please refer to [7:2] bits of the offset 7Ch – Register Page 2. If the

CH7036’s VGA output feature has been intentionally disabled by the system manufacture, the detection mechanism

can be switched off by setting the SPPSNS bit to “1” for reducing power dissipation.

2.3.5 Picture enhancement

CHRONTEL

CH7036

201-1000-009 Rev. 1.24, 08/15/2011 13

The horizontal and the vertical positions of the VGA display can be adjusted through offsets 39h, 3Ah and 3Bh -

“0” first; the sharpness of the display text will reflect upon the value in the [2:0] of the offset 2Eh - Register Page 1.

2.4 HDMI/DVI Output

The device’s HDMI/DVI link includes three TMDS Data channels and a single TMDS Clock channel. The TMDS

Clock channel constantly runs at the pixel rate of the transmitted video. During every cycle of the TMDS Clock

channel, each of the three TMDS data channels transmits a 10-bit character. This 10-bit word is encoded using one

of several different coding techniques.

The order of HDMI output pins can be swapped by setting bits[ 4:0], the offset 4Ch – Register Page 1:

Table 5: CH7036 HDMI Output Pins Mapping

HD_LV_SEQ[4:0] DATA0 DATA1 DATA2 CLOCK

0 0 1 2 3

1 0 1 3 2

2 0 2 1 3

3 0 2 3 1

4 0 3 1 2

5 0 3 2 1

6 1 0 2 3

7 1 0 3 2

8 1 2 3 0

9 1 2 0 3

10 1 3 2 0

11 1 3 0 2

12 2 0 1 3

13 2 0 3 1

14 2 1 0 3

15 2 1 3 0

16 2 3 0 1

17 2 3 1 0

18 3 0 1 2

19 3 0 2 1

20 3 1 0 2

21 3 1 2 0

22 3 2 0 1

23 3 2 1 0

In addition, toggling the bit 5 of the same register will invert the polarity of HDMI output’s clock and data. Altering

the HSync and Vsync polarities can be achieved by programming the bit-6 and the bit-5 of the offset 61h – Register

Page 4 accordingly.

2.5 LVDS Output

There are 4 pairs serial data lines (LDC0 through LDC3) and one pair serial clock lines (LLC) in the CH7036’s

LVDS output. The serial data stream on each signal line shall be at a bit rate that is seven times the pixel rate. The

LVDS output supports 18-bit/24-bit (Figure 7,8) single pixel format defined by the SPWG specification.

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