Recommendation X.25 (10/96) 9
2.2.7.3 Information field
The information field of a frame, when present, follows the control field (see 2.2.7.2 above) and precedes the frame
check sequence field (see 2.2.7.4 below).
For start/stop transmission there shall be eight (8) information bits between the start bit and the stop bit.
When transmitting from the DCE to the DTE, if the information to be inserted in the information field does not have a
number of bits that is multiple of 8, the DCE shall pad this information field with zeros so that the information field will
be octet-aligned.
When transmitting from the DTE to the DCE, the DTE shall transmit only octet-aligned information.
See 2.3.4.9, 2.5.2 and clause 5 for the various codings and groupings of bits in the information field as used in this
Recommendation.
See 2.3.4.9 and 2.4.9.5 below with regard to the maximum information field length.
2.2.7.4 Frame Check Sequence (FCS) field
The notation used to describe the FCS is based on the property of cyclic codes that a code vector such as
1000000100001 can be represented by a polynomial P(x)
=
x
12
+
x
5
+
1. The elements of an n-element code word are
thus the coefficients of a polynomial of order n – 1. In this application, these coefficients can have the value 0 or 1 and
the polynomial operations are performed modulo 2. The polynomial representing the content of a frame is generated
using the first bit received after the frame opening flag as the coefficient of the highest order term.
The FCS field shall be a 16-bit sequence. It shall be the ones complement of the sum (modulo 2) of:
1) the remainder of x
k
(x
15
+
x
14
+
x
13
+
x
12
+
x
11
+
x
10
+
x
9
+
x
8
+ x
7
+
x
6
+
x
5
+
x
4
+
x
3
+
x
2
+
x
+
1)
divided (modulo 2) by the generator polynomial x
16
+
x
12
+
x
5
+
1, where k is the number of bits in the
frame existing between, but not including, the final bit of the opening flag and the first bit of the FCS,
excluding bits (synchronous transmission) or octets (start/stop transmission) inserted for transparency,
and bits inserted for transmission timing (i.e. start or stop bits); and
2) the remainder of the division (modulo 2) by the generator polynomial x
16
+
x
12
+
x
5
+
1 of the product of
x
16
by the content of the frame, existing between but not including, the final bit of the opening flag and
the first bit of the FCS, excluding bits (synchronous transmission) or octets (start/stop transmission)
inserted for transparency and bits inserted for transmission timing (i.e. start or stop bits).
As a typical implementation, at the transmitter, the initial content of the register of the device computing the remainder
of the division is preset to all 1s and is then modified by division by the generator polynomial (as described above) on
the address, control and information fields; the ones complement of the resulting remainder is transmitted as the 16-bit
FCS.
At the receiver, the initial content of the register of the device computing the remainder is preset to all 1s. The final
remainder, after multiplication by x
16
and then division (modulo 2) by the generator polynomial x
16
+
x
12
+
x
5
+
1 of the
serial incoming protected bits and the FCS, will be 0001110100001111 (x
15
through x
0
, respectively) in the absence of
transmission errors.
NOTE – Examples of transmitted bit patterns by the DCE and the DTE illustrating application of the transparency
mechanism and the frame check sequence to the SABM command and the UA response are given in Appendix I.
2.3 LAPB elements of procedures
2.3.1 The LAPB elements of procedures are defined in terms of actions that occur on receipt of frames at the DCE
or DTE.
The elements of procedures specified below contain the selection of commands and responses relevant to the LAPB data
link and system configurations described in 2.1 above. Together, 2.2 and 2.3 form the general requirements for the
proper management of an LAPB access data link.