VHDL编程实践：从基础逻辑到复杂系统

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"本资源为VHDL编程实例集合，由Ian Elliot of Northumbria University提供，展示了VHDL在描述各种硬件时的多样性和强大功能。实例涵盖了从基础组合逻辑（通过基本逻辑门描述）到更复杂的系统，如微处理器的行为模型和相关内存。所有示例都可以使用符合IEEE标准的VHDL模拟器进行仿真，许多还可以用当前的综合工具进行综合实现。" 详细知识点: 1. **VHDL语言基础**：VHDL是一种硬件描述语言，用于描述数字系统的结构和行为。它允许工程师以数据流、行为和结构三种风格编写代码。 2. **组合逻辑**： - **数据流风格**：以操作符和信号之间的关系来描述电路，如Exclusive-OR门的数据流实现。 - **行为风格**：基于算法描述逻辑，比如Exclusive-OR门的行为方式实现。 - **结构风格**：使用基本逻辑门构建复杂逻辑，如Exclusive-OR门的结构化实现。 - **其他逻辑门**：包括各种逻辑门的实现，如多数表决器、比较器和解码器。 3. **计数器**：VHDL可以用来设计各种类型的计数器，如二进制计数器、模n计数器等，这些都是数字系统中的常见组件。 4. **移位寄存器**：用于存储和移动数据，是串行数据处理的基础。 5. **内存**：VHDL能描述不同类型的存储器，如RAM、ROM、FIFO等，对于实现数据存储和处理至关重要。 6. **状态机**：VHDL中的状态机设计是控制逻辑的核心，常用于描述序列事件和决策流程。 7. **寄存器**：VHDL中的寄存器用于临时存储数据，是数字系统中的关键元素。 8. **系统设计**：VHDL可以描述整个系统级别的设计，包括微处理器的抽象行为模型。 9. **模数转换器（ADC）与数模转换器（DAC）**：这些是模拟和数字世界之间的桥梁，VHDL可以用来设计它们的接口和控制逻辑。 10. **算术运算**：VHDL支持各种算术运算的描述，例如加法器、乘法器等，对于数字计算和信号处理至关重要。 11. **总线接口**：如八位总线收发器，用于设备间的数据传输和通信。这些实例为学习和理解VHDL提供了丰富的素材，帮助工程师从基础到高级逐步掌握VHDL的设计技巧，进而能够设计复杂的数字系统。通过这些实例，可以模拟、验证并最终实现硬件电路，加深对VHDL编程的理解。

Examples of VHDL Descriptions

tin(i) <= '1';

end generate;

t1_size : if i > 0 generate

tin(i) <= q(i-1) and tin(i-1);

end generate;

end v1;

Counter using Multiple Wait Statements

This example shows an inefficient way of describing a counter.

--vhdl model of a 3-state counter illustrating the use

--of the WAIT statement to suspend a process.At each wait

--statement the simulation time is updated one cycle,transferring

--the driver value to the output count.

--This architecture shows that there is no difference between

--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'

ENTITY cntr3 IS

PORT(clock : IN BIT; count : OUT NATURAL);

END cntr3;

ARCHITECTURE using_wait OF cntr3 IS

BEGIN

PROCESS

BEGIN

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 2;

END PROCESS;

END using_wait;

Counter using a Conversion Function

This counter uses a natural number to hold the count value and converts it into a bit_vector for output. Illustrates the use of a function.

--4-bit binary up counter with asynchronous reset 2/2/93

ENTITY cntr4bit IS

PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));

END cntr4bit;

ARCHITECTURE dataflow OF cntr4bit IS

--interface function to generate output bit_vector from

--internal count value.

FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)

RETURN BIT_VECTOR IS

VARIABLE temp : NATURAL := 0;

VARIABLE output : BIT_VECTOR(0 TO highbit);

BEGIN

temp := input;

--check that input fits into (highbit+1) bits

ASSERT (temp <= (2**(highbit + 1) - 1))

REPORT "input no. is out of range" SEVERITY ERROR;

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Examples of VHDL Descriptions

--generate bit values

FOR i IN highbit DOWNTO 0 LOOP

IF temp >= (2**i)

THEN output(i) := '1';

temp := temp - (2**i);

ELSE output(i) := '0';

END IF;

END LOOP;

RETURN output;

END nat_to_bv;

--signal to hold current count value

SIGNAL intcount : NATURAL := 0;

BEGIN

--conditional natural signal assignment models counter

intcount <= 0 WHEN (reset = '1') ELSE

((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')

ELSE intcount;

--interface function converts natural count to bit_vector count

count <= nat_to_bv(intcount,3);

END;

Quad 2-input Nand

Simple concurrent model of a TTL quad nand gate.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT00 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT00;

architecture VER1 of HCT00 is

begin

Y1 <= A1 nand B1 after 10 ns;

Y2 <= A2 nand B2 after 10 ns;

Y3 <= A3 nand B3 after 10 ns;

Y4 <= A4 nand B4 after 10 ns;

end VER1;

Dual 2-to-4 Decoder

A set of conditional signal assignments model a dual 2-to-4 decoder

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT139 is

port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;

Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);

end HCT139;

architecture VER1 of HCT139 is

begin

Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';

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Examples of VHDL Descriptions

Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';

Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';

Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end VER1;

Quad D-Type Flip-flop

This example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part

of the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is

port(D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0);

CLRBAR, CLK : in std_logic);

end HCT175;

architecture VER1 of HCT175 is

begin

Q <= (others => '0') when (CLRBAR = '0')

else D when rising_edge(CLK)

else unaffected;

end VER1;

Octal Bus Transceiver

This example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than

std_ulogic).

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT245 is

port(A, B : inout std_logic_vector(7 downto 0);

DIR, GBAR : in std_logic);

end HCT245;

architecture VER1 of HCT245 is

begin

A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');

B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');

end VER1;

Quad 2-input OR

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT32 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT32;

architecture VER1 of HCT32 is

begin

Y1 <= A1 or B1 after 10 ns;

Y2 <= A2 or B2 after 10 ns;

Y3 <= A3 or B3 after 10 ns;

Y4 <= A4 or B4 after 10 ns;

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