NANYA Technology DDR2-1GB SDRAM规格介绍

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NT5TU64M16DG.pdf文件主要介绍了1GB(1 Gb) DDR2双数据速率（Double-Data-Rate 2，简称DDR2）动态随机存取内存(DRAM)模块。这种高速CMOS DRAM包含1,073,741,824位，内部配置为八银行结构。它具有多种规格，包括不同频率和 CAS latency（列地址有效时间）、RAS（Row Address Strobe，行地址使能）时间和RP（RAS Precharge，行预充电）时间，以支持不同的工作模式。 DDR2-533、DDR2-667、DDR2-800以及DDR2-1066等频率选项，分别对应着不同的时序参数，如tRCD（列地址到数据传输时间）、tRP（行预充电时间）、tRC（行刷新时间）和tRAS（行有效时间）。这些时序参数对于确保内存性能稳定、降低功耗和提高系统效率至关重要。例如，随着时钟频率的提升，时序值可能会有所减少，以适应更高的数据传输速度。文件还提到，内存模块支持从CL（Cas Latency）3到CL7的不同级别，这意味着在不同CAS延迟下，平均时钟周期(tCK)也有相应的调整。此外，这款内存供电电压为1.8V±0.1V，且具有可编程性，允许根据系统需求进行配置。 NT5TU64M16DG系列还包括NT5TU256M4DE和NT5TU128M8DE，这些都是相同类型的内存，但容量不同，分别提供256MB和128MB。该系列产品的设计目标是满足消费者级应用，更新日期为2009年11月，由纳尼亚科技公司(Nanya Technology Corp.)制造并保留所有权利，声明产品规格可能随时变更而无需通知。 NT5TU64M16DG是一款高性能的DDR2内存，适用于需要高速数据传输和低延迟的计算机系统，其特性决定了它在现代计算机架构中的关键角色。理解这些参数对于优化内存子系统的性能和稳定性至关重要。

NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG

1Gb DDR2 SDRAM

REV 1.8 CONSUMER DRAM

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

MRS Mode Register Operation Table (Address Input for Mode Set)

A0A1A2A3A4A5A6A7A8A9A10A11A12A13BA0BA1BA2

Address Field

BLA0A1A2

4010

8110

Burst Length

Burst TypeA3

Sequential0

Interleave

Burst Type

CAS LatencyA4A5A6

Reserved000

Reserved100

/CAS Latency

010

110

001

101

011

111

Reserved

MRS mode

BA0BA1

EMR(1)

MRS mode

EMR(3)

EMR(2)

Active power down

exit time

A12

Fast exit (use tXARD)0

Slow exit (use tXARDS)

Active power down exit

time

* *

WR(cycles)A9A10A11

Reserved000

2100

Write recovery for autoprecharge

010

110

001

101

011

111

DLL ResetA8

NO0

YES

DLL Reset

ModeA7

Normal0

TEST

Mode

* BA2 and A13 are reserved for future use and must be set to

"0" when programming MR.

DDR2-1066

DDR2-667

DDR2-800

DDR2-533

Reserved

NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG

1Gb DDR2 SDRAM

REV 1.8 CONSUMER DRAM

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register Set –EMRS (1)

The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive

latency, ODT,  disable, OCD program, RQDS enable. The default value of the extended mode register EMRS(1) is

not defined, therefore the extended mode register must be written after power-up for proper operation. The extended

mode register is written by asserting low on , , , , BA1 and high on BA0, while controlling the state of the

address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended

mode register. The mode register set command cycle time (t

MRD

) must be satisfied to complete the write operation to the

EMRS (1). Mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD control, A10 is used for 

disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.

Single-ended and Differential Data Strobe Signals

The following table lists all possible combinations for DQS, , RDQS,  which can be programmed by A10 & A11

address bits in EMRS(1). RDQS and  are available in x8 components only. If RDQS is enabled in x8 components,

the DM function is disabled. RDQS is active for reads and don‟t care for writes.

EMRS(1)

Strobe Function Matrix

A11

(RDQS Enable)

A10

( Enable)

RDQS/DM



DQS



Signaling

0 (Disable)

0 (Enable)

Hi-Z

DQS



differential DQS signals

0 (Disable)

1 (Disable)

Hi-Z

DQS

Hi-Z

single-ended DQS signals

1 (Enable)

0 (Enable)

RDQS



DQS



differential DQS signals

1 (Enable)

1 (Disable)

RDQS

Hi-Z

DQS

Hi-Z

single-ended DQS signals

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning

to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh

operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset,

200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be

synchronized with the external clock. Less clock cycles may result in a violation of the t

or t

DQSCK

parameters.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Q

off

bit in the EMRS (1) is

set to 0). When the Q

off

bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to

measure I

currents during Read operations, without including the output buffer current and external load currents.

NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG

1Gb DDR2 SDRAM

REV 1.8 CONSUMER DRAM

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

EMRS(2) Extended Mode Register Set Programming

Address Field

Extended Mode

PASR***

BA1

BA0

A11

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A2 A1 A0

Partial Array Self Refresh

0 0 0

Full array

0 0 1

Half Array (BA[2:0]=000, 001, 010, &011)

0 1 0

Quarter Array (BA[2:0]=000&001)

0 1 1

1/8

array (BA[2:0] = 000)

1 0 0

3 / 4 array (BA[2:0]=010,011,100,101,110, &111)

1 0 1

Half array (BA[2:0]=100, 101, 110, & 111)

1 1 0

Quarter array (BA[2:0]=110&111)

1 1 1 1/8

array (BA[2:0]=111)

SRF

0 Disable

1 Enable** (85C Tcase 95C)

High Temperature Self-Refresh Rate Enable

A12

BA2

BA0

MRS mode

0 MRS

EMRS(1)

BA1

EMRS(2)

EMRS(3):

Reserved

* The rest bits in EMRS(2) is reserved for future use and all bits in EMRS(2) except A0-A2,A7,BA0, and

BA1 must be programmed to 0 when setting EMRS(2) during initialization.

** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].

*** Optional. If PASR(Partial Array Self Refresh) is enabled, data located in areas of the array beyond the

spec. location will be lost if self refresh is entered.

Extended Mode Register Set EMRS (2)

The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is

not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1,

while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already

high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be

satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using

the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.

EMRS(3) Extended Mode Register Set Programming

All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode

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