SystemVerilog综合设计： ASIC和FPGA设计的RTL模型

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SystemVerilog综合设计 SystemVerilog是一种功能强大的硬件描述语言，既可以用来验证，也可以用于芯片硬件开发。近年来，SystemVerilog在ASIC和FPGA设计中的应用日益广泛。然而，使用SystemVerilog进行综合设计需要具备一定的策略和技术。下面，我们将详细介绍SystemVerilog在综合设计中的应用和优势。 SystemVerilog的历史 -------------------- SystemVerilog是Verilog的继承者，于2002年发布。它的主要目的是为了满足硬件设计的需求，提高设计效率和设计质量。SystemVerilog标准于2005年发布，自此成为ASIC和FPGA设计的 industry standard。 SystemVerilog的特点 -------------------- SystemVerilog与Verilog相比，有以下几个特点： * 面向对象的设计：SystemVerilog支持面向对象的设计方法，提高了设计的灵活性和可重用性。 * 高级抽象：SystemVerilog提供了高级抽象的设计方法，能够描述复杂的硬件系统。 * 综合设计：SystemVerilog支持综合设计，能够将设计模型转换为可实施的硬件语言。 SystemVerilog在综合设计中的应用 -------------------------------- SystemVerilog在综合设计中的应用主要包括以下几个方面： * RTL设计：SystemVerilog可以用来设计RTL（Register-Transfer Level），提高设计效率和设计质量。 * ASIC设计：SystemVerilog可以用来设计ASIC（Application-Specific Integrated Circuit），提高设计效率和设计质量。 * FPGA设计：SystemVerilog可以用来设计FPGA（Field-Programmable Gate Array），提高设计效率和设计质量。 SystemVerilog的优势 -------------------- SystemVerilog在综合设计中的优势包括： * 高效设计：SystemVerilog可以提高设计效率，减少设计时间和成本。 * 高质量设计：SystemVerilog可以提高设计质量，减少设计错误和 Bug。 * 灵活设计：SystemVerilog可以提高设计灵活性，满足不同设计需求。 SystemVerilog的设计工具 ------------------------- SystemVerilog有多种设计工具，包括： * Design Compiler：是Synopsys公司推出的一个综合设计工具，支持SystemVerilog语言。 * Synplify-Pro：是Synopsys公司推出的一个综合设计工具，支持SystemVerilog语言。结语 ---- SystemVerilog是一种功能强大的硬件描述语言，能够提高设计效率和设计质量。在ASIC和FPGA设计中，SystemVerilog的应用日益广泛。然而，使用SystemVerilog进行综合设计需要具备一定的策略和技术。通过本文，我们了解了SystemVerilog在综合设计中的应用和优势，希望能够帮助读者更好地理解和应用SystemVerilog。

SNUG Silicon Valley 2013 8 Synthesizing SystemVerilog

Array copy assignments require that the number of dimensions and the number of elements in each

dimension be identical on both sides of the assignment. The number of bits of each element must also be

the same size and of compatible data types. Array copy assignments are synthesizable, and can

significantly reduce the complexity of design code for moving blocks of data from one array to another.

2.5.3 Assigning value lists to arrays

All or multiple elements of an array can be assigned using a list of values, enclosed in ’{ }. The list can

contain values for an individual array element, or a default value for the entire array.

logic [7:0] a, b, c;

logic [7:0] d_array [0:3]; // array with 4 32-bit elements

always_ff @(posedge clock or negedge rstN)

if (!rstN) d_array <= ’{default:0}; // reset all elements of the array

else d_array <= ’{8’h00, c, b, a}; // load the array

Array lists are synthesizable. The number of array dimensions and the number of values in the array list

must be identical. The number of bits of each element must also be the same size as the values in the list.

2.5.4 Passing arrays through module ports and to tasks and functions

The ability to assign to multiple elements of an array also makes it possible to use arrays as module ports

or task/function arguments. The following example defines a user-defined type that represents a 8x256 2-

dimensional array of 32-bit elements, and then passes that array to and from a function, and through

module ports. Section 2.6 discusses user-defined types in more detail, and section 4.1 discusses the

appropriate place to define user-defined types.

typedef logic [31:0] d_array_t [0:7][0:255];

module block_data (input d_array_t d_in, // input is an array

output d_array_t q_out, // output is an array

input logic clock, rstN);

function d_array_t transform (input d_array_t d); // input is an array

// ... perform operations on all elements of d

return d; // return is an array

endfunction

always_ff @(posedge clock or negedge rstN)

if (!rstN) q_out <= ’{default:0}; // reset entire q_out array

else q_out <= transform(d_in); // transform and store entire array

endmodule

Note that SystemVerilog requires that the values passed through an array port or task/function argument

have the same number of dimensions, and that each element be the same vector size and a compatible type.

2.5.5 Array query system functions

SystemVerilog provides a number of special system functions that make it easier to manipulate an array

without hard coding the size of the array. The synthesizable array query functions are:

$left(),

$right(), $low(), $high(), $increment(), $size(), $dimensions(), and

$unpacked_dimensions(). Following is an example of using some of these functions:

SNUG Silicon Valley 2013 9 Synthesizing SystemVerilog

typedef logic [31:0] d_array_t [0:15][0:15];

function d_array_t transform (input d_array_t d);

for (int i = $low(d,1); i <= $high(d,1); i++) begin: outer_loop

for (int j = $low(d,2); j <= $high(d,2); j++) begin: inner_loop

// ... perform some sort of operation on each element of d

end: inner_loop

end: outer_loop

return d; // function return is an array

endfunction

Note: This example could be significantly simplified by using a foreach loop. Unfortunately, foreach is

not supported by DC or Synplify-Pro. See section 12.2 for more details on

foreach loops.

2.5.6 Non-synthesizable array enhancements

SystemVerilog extends Verilog arrays in several other ways that are not synthesizable. These

enhancements include a

foreach array iterator loop, array operation functions, array locator functions,

array sorting functions, and array bit-stream casting.

2.6 User-defined types

The original Verilog language only had built-in data types. SystemVerilog allows design and verification

engineers to create new, user-defined data types. Both variables and nets can be declared as user-defined

types. If neither the

var or a net type keyword is specified, then user-defined types are assumed to be

variables. The synthesizable user-defined types are:

• enum — variables or nets with an enumerated list of legal values — see section 2.6.1

• struct — a structure comprising multiple nets or variables — see section 2.6.2

• union — a variable that can represent different types at different times — see section 2.6.3

•

typedef — type definitions — see section 2.6.4

2.6.1 Enumerated types

Enumerated types allow variables and nets to be defined with a specific set of named values. Only the

synthesizable aspects of enumerated types are presented in this paper. The basic syntax for declaring an

enumerated type is:

// a variable that has 3 legal values

enum {WAITE, LOAD, DONE} State;

Enumerated types have a base data type, which, by default, is int (a 2-state, 32-bit type). In the example

above,

State is an int type, and WAITE, LOAD and DONE will have 32-bit int values. The labels in the

enumerated list are constants that have an associated logic value. By default, the first label in the list has a

logic value of 0, and each subsequent label is incremented by one. Thus, in the example above,

WAITE is 0,

LOAD is 1, and DONE is 2.

Designers can specify an explicit base type, allowing enumerated types to more specifically model

hardware. Designers can specify explicit values for any or all labels in the enumerated list. An example is:

// Two 3-bit, 4-state enumerated variables with one-hot values

enum logic [2:0] {WAITE = 3’b001,

LOAD = 3’b010,

DONE = 3’b100} State, NextState;

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