SNUG Silicon Valley 2013 8 Synthesizing SystemVerilog
Array copy assignments require that the number of dimensions and the number of elements in each
dimension be identical on both sides of the assignment. The number of bits of each element must also be
the same size and of compatible data types. Array copy assignments are synthesizable, and can
significantly reduce the complexity of design code for moving blocks of data from one array to another.
2.5.3 Assigning value lists to arrays
All or multiple elements of an array can be assigned using a list of values, enclosed in ’{ }. The list can
contain values for an individual array element, or a default value for the entire array.
logic [7:0] a, b, c;
logic [7:0] d_array [0:3]; // array with 4 32-bit elements
always_ff @(posedge clock or negedge rstN)
if (!rstN) d_array <= ’{default:0}; // reset all elements of the array
else d_array <= ’{8’h00, c, b, a}; // load the array
Array lists are synthesizable. The number of array dimensions and the number of values in the array list
must be identical. The number of bits of each element must also be the same size as the values in the list.
2.5.4 Passing arrays through module ports and to tasks and functions
The ability to assign to multiple elements of an array also makes it possible to use arrays as module ports
or task/function arguments. The following example defines a user-defined type that represents a 8x256 2-
dimensional array of 32-bit elements, and then passes that array to and from a function, and through
module ports. Section 2.6 discusses user-defined types in more detail, and section 4.1 discusses the
appropriate place to define user-defined types.
typedef logic [31:0] d_array_t [0:7][0:255];
module block_data (input d_array_t d_in, // input is an array
output d_array_t q_out, // output is an array
input logic clock, rstN);
function d_array_t transform (input d_array_t d); // input is an array
// ... perform operations on all elements of d
return d; // return is an array
endfunction
always_ff @(posedge clock or negedge rstN)
if (!rstN) q_out <= ’{default:0}; // reset entire q_out array
else q_out <= transform(d_in); // transform and store entire array
endmodule
Note that SystemVerilog requires that the values passed through an array port or task/function argument
have the same number of dimensions, and that each element be the same vector size and a compatible type.
2.5.5 Array query system functions
SystemVerilog provides a number of special system functions that make it easier to manipulate an array
without hard coding the size of the array. The synthesizable array query functions are:
$left(),
$right(), $low(), $high(), $increment(), $size(), $dimensions(), and
$unpacked_dimensions(). Following is an example of using some of these functions:
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