Hi3518E SoC技术规格：720p IP摄像头数据手册

Hi3518E

datasheet

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"本文档是Hi3518E 720p IP Camera SoC的数据手册，由海思半导体科技有限公司在2014年3月27日发布。内容涵盖芯片的模块特性、逻辑结构、工作模式、寄存器信息、接口时序、引脚定义、性能参数及封装等关键信息。请注意，此文档提供的所有产品、服务和特性可能并不全部包含在购买或使用范围内，且不提供任何形式的明示或暗示保证。" Hi3518E是一款专用于720p高清网络摄像头的系统级芯片（SoC），其设计旨在集成图像处理、编码和网络连接等功能，以实现高效、高质量的视频监控解决方案。以下是对该SoC的一些核心知识点的详细说明： 1. **模块特性**：Hi3518E集成了高分辨率视频编码器，支持720p分辨率，可以处理来自CMOS或CCD传感器的图像数据。此外，它还包含了数字信号处理单元（DSP）用于图像增强和噪声抑制，确保在不同光照条件下都能获取清晰的图像。 2. **逻辑结构**：芯片内部结构包括图像信号处理器（ISP）、视频编码器、网络处理器、内存接口以及各种外围接口。ISP负责图像预处理，如白平衡、色彩校正和曝光控制；视频编码器则将处理后的图像数据压缩成H.264或MJPEG等格式，便于网络传输。 3. **工作模式**：Hi3518E支持多种工作模式，如连续视频流模式、抓帧模式和低功耗模式，可以根据应用需求灵活切换，以优化能效和性能。 4. **接口时序和参数**：文档详细描述了与外部设备如传感器、存储器和网络接口的通信协议，包括I2C、SPI、MIPI-CSI等，以及相关时序参数，这对于正确配置和调试系统至关重要。 5. **引脚定义和封装**：Hi3518E的引脚功能和封装信息提供了硬件设计的基础，包括电源、接地、输入/输出、控制信号等，设计者可以根据这些信息进行PCB布局和系统级集成。 6. **性能参数**：这些参数包括工作电压、功耗、温度范围、最大时钟频率等，对于评估芯片在实际环境下的性能和稳定性有着重要意义。 7. **法律条款**：文档最后强调，未经许可，任何部分不得复制或传播，所有商标均归各自所有者所有，且产品和服务的具体内容以购买合同为准。 Hi3518E 720p IP Camera SoC是一款高度集成的解决方案，适用于设计高性能、低功耗的网络摄像头。开发者和硬件工程师可以根据此数据手册提供的信息进行系统设计和优化。

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Hi3518E 720p IP Camera SoC

Data Sheet 1 Introduction

Issue 00B02 (2014-03-27)

HiSilicon Proprietary and Confidential

1-6

Start

Address

End Address Function Capacity Remarks

0x8000_0000 0x8FFF_FFFF Address space for connecting the

DDR to an external DDR

256 MB None

0x5C00_0000 0x7FFF_FFFF Reserved None None

0x5800_0000 0x5BFF_FFFF Storage space of the SPI flash 64 MB None

0x5000_0000 0x57FF_FFFF Reserved None None

0x206E_0000 0x4FFF_FFFF Reserved None None

0x206D_0000 0x206D_FFFF DDR test module 64 KB None

0x206C_0000 0x206C_FFFF Motion detection (MD) register 64 KB None

0x2067_0000 0x206B_FFFF Reserved None None

0x2066_0000 0x2066_FFFF JPEG encoder (JPGE) register 64 KB None

0x2063_0000 0x2065_FFFF Reserved None None

0x2062_0000 0x2062_FFFF Video encoding (VENC) register 64 KB None

0x2061_0000 0x2061_FFFF Two-dimensional engine (TDE)

64 KB None

0x2060_0000 0x2060_FFFF Video process subsystem (VPSS)

64 KB None

0x205F_0000 0x205F_FFFF Reserved None None

0x205E_0000 0x205E_FFFF IVE register 64 KB None

0x205D_0000 0x205D_FFFF Reserved None None

0x205C_0000 0x205C_FFFF Video display (VDP) register 64 KB None

0x2058_0000 0x205B_FFFF Video capture (VICAP) register 256 KB None

0x2020_0000 0x2057_FFFF Reserved None None

0x201F_0000 0x201F_FFFF GPIO11 register 64 KB None

0x201E_0000 0x201E_FFFF GPIO10 register 64 KB None

0x201D_0000 0x201D_FFFF GPIO9 register 64 KB None

0x201C_0000 0x201C_FFFF Reserved None None

0x201B_0000 0x201B_FFFF GPIO7 register 64 KB None

0x201A_0000 0x201A_FFFF GPIO6 register 64 KB None

0x2019_0000 0x2019_FFFF GPIO5 register 64 KB None

0x2018_0000 0x2018_FFFF GPIO4 register 64 KB None

0x2017_0000 0x2017_FFFF GPIO3 register 64 KB None

Hi3518E 720p IP Camera SoC

Data Sheet Contents

Issue 00B02 (2014-03-27)

HiSilicon Proprietary and Confidential

Contents

2 Hardware ..................................................................................................................................... 2-1

2.1 Package and Pinout ....................................................................................................................................... 2-1

2.1.1 Package ................................................................................................................................................ 2-1

2.1.2 Pinout ................................................................................................................................................... 2-3

2.2 Pin Descriptions ............................................................................................................................................ 2-9

2.2.1 Pin Types .............................................................................................................................................. 2-9

2.2.2 Pin Details .......................................................................................................................................... 2-10

2.3 Pin Multiplexing Control Registers ............................................................................................................. 2-31

2.3.1 Summary of Multiplexing Control Registers ..................................................................................... 2-31

2.3.2 Register Description ........................................................................................................................... 2-35

2.4 Software Multiplexed Pins .......................................................................................................................... 2-76

2.5 Hardware Multiplexed Pins ......................................................................................................................... 2-92

2.6 Electrical Specifications .............................................................................................................................. 2-93

2.6.1 Power Consumption Specifications ................................................................................................... 2-93

2.6.2 Temperature and Thermal Resistance Parameters .............................................................................. 2-94

2.6.3 Working Conditions ........................................................................................................................... 2-94

2.6.4 DC and AC Electrical Specifications ................................................................................................. 2-95

2.6.5 Power-On and Power-Off Sequence .................................................................................................. 2-96

2.7 PCB Design Recommendations .................................................................................................................. 2-96

2.8 Interface Timings ........................................................................................................................................ 2-96

2.8.1 SFC Interface Timings ....................................................................................................................... 2-96

2.8.2 Ethernet MAC Port Timings .............................................................................................................. 2-97

2.8.3 VI Interface Timing .......................................................................................................................... 2-102

2.8.4 VO Interface Timing ........................................................................................................................ 2-103

2.8.5 SIO Interface Timings ...................................................................................................................... 2-103

2.8.6 I

C Interface Timing......................................................................................................................... 2-104

2.8.7 SPI Timings ...................................................................................................................................... 2-105

Hi3518E 720p IP Camera SoC

Data Sheet Figures

Issue 00B02 (2014-03-27)

HiSilicon Proprietary and Confidential

Figures

Figure 2-1 Top view ........................................................................................................................................... 2-1

Figure 2-2 Bottom view ..................................................................................................................................... 2-2

Figure 2-3 Side view .......................................................................................................................................... 2-2

Figure 2-4 Enlarged view of detail "A" .............................................................................................................. 2-2

Figure 2-5 Pin map ............................................................................................................................................. 2-5

Figure 2-6 SFC input timing............................................................................................................................. 2-97

Figure 2-7 SFC output timing ........................................................................................................................... 2-97

Figure 2-8 100 Mbit/s RX timing of the MII .................................................................................................... 2-98

Figure 2-9 100 Mbit/s TX timing of the MII .................................................................................................... 2-98

Figure 2-10 10 Mbit/s RX timing of the MII .................................................................................................... 2-98

Figure 2-11 10 Mbit/s TX timing of the MII .................................................................................................... 2-98

Figure 2-12 RX timing parameters of the MII.................................................................................................. 2-99

Figure 2-13 TX timing parameters of the MII .................................................................................................. 2-99

Figure 2-14 100 Mbit/s RX timing of the RMII ............................................................................................. 2-100

Figure 2-15 100 Mbit/s TX timing of the RMII ............................................................................................. 2-100

Figure 2-16 10 Mbit/s RX timing of the RMII ............................................................................................... 2-100

Figure 2-17 10 Mbit/s TX timing of the RMII ............................................................................................... 2-100

Figure 2-18 Timing parameters of the RMII .................................................................................................. 2-101

Figure 2-19 Read timing of the MDIO interface ............................................................................................ 2-101

Figure 2-20 Write timing of the MDIO interface ........................................................................................... 2-102

Figure 2-21 RX timing parameters of the MDIO interface ............................................................................ 2-102

Figure 2-22 VI interface timing ...................................................................................................................... 2-103

Figure 2-23 VO interface timing .................................................................................................................... 2-103

Figure 2-24 I

S interface RX timing ............................................................................................................... 2-104

Figure 2-25 I

S interface TX timing ............................................................................................................... 2-104

Figure 2-26 I2C transfer timing ...................................................................................................................... 2-104