STM32F107系列：全能ARM微控制器，集成丰富功能

需积分: 31 178 浏览量更新于2024-07-20 收藏 1.53MB PDF 举报

本文档详细介绍了一款实用型STM32F107xx系列微控制器，该系列属于ARM架构的32位微处理器，专为连接性、高效能应用设计。STM32F105xx和STM32F107xx型号提供了64到256KB的闪存和64KB的通用型静态随机访问存储器(SRAM)，以满足不同项目的需求。核心部分采用的是ARM Cortex-M3处理器，其最大工作频率可达72MHz，具有出色的性能表现，尤其是在处于等待状态时，内存访问只需单个周期。这款芯片支持硬件乘法和除法运算，有助于提高计算效率。在存储方面，该设备提供了丰富的选项，包括内部的8MHz工厂预调整的RC振荡器，以及可进行校准的40kHz RC振荡器和32kHz用于实时时钟(RTC)的振荡器。此外，还配备了64至256KB的Flash存储空间，以储存程序代码和数据。低功耗是STM32F107xx的重要特性，支持多种省电模式，如睡眠、停机和待机，使得在需要降低能耗的应用中也能保持良好的运行效率。特别地，它还提供了一个VBAT备用电源，确保RTC和备份寄存器在无主电源时仍能维持正常工作。集成的数字信号处理能力强大，包括两个12位的模拟到数字转换器(ADC)，分辨率高达1μs，可以测量电压范围从0到3.6V，并具备采样保持功能，以及用于温度检测的特性。同时，还有两个12位的数字到模拟转换器(DAC)。值得一提的是，STM32F107xx内置了12通道的直接内存访问(DMA)控制器，能够高效地处理数据传输任务，支持与定时器、ADC、DAC、I2S、SPI和I2C等多种外设的连接，极大地简化了系统的数据通信和控制操作。 STM32F107xx系列微控制器因其高性能、多样化的内存配置、低功耗特性和丰富的接口选项，成为工业控制、嵌入式系统设计以及物联网(IoT)等领域的理想选择。通过阅读这份文档，开发者可以深入了解如何充分利用这些特性来构建高效、灵活的解决方案。

Description STM32F105xx, STM32F107xx

16/104 Doc ID 15274 Rev 6

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose, basic

and advanced control timers TIMx, DAC, I

S and ADC.

In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see

Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for

more information).

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

For more information, please refer to AN2604: “STM32F101xx and STM32F103xx RTC

calibration”, available from www.st.com.

STM32F105xx, STM32F107xx Description

Doc ID 15274 Rev 6 17/104

2.3.15 Timers and watchdogs

The STM32F105xx and STM32F107xx devices include an advanced-control timer, four

general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Tabl e 4 compares the features of the general-purpose and basic timers.

Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6

channels. It has complementary PWM outputs with programmable inserted dead-times. It

can also be seen as a complete general-purpose timer. The 4 independent channels can be

used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes)

● One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same

architecture. The advanced control timer can therefore work together with the TIM timers via

the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded

in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based

on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent

channels each for input capture/output compare, PWM or one pulse mode output. This

gives up to 16 input captures / output compares / PWMs on the largest packages. They can

work together with the Advanced Control timer via the Timer Link feature for synchronization

or event chaining.

The counter can be frozen in debug mode.

Table 4. Timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM1 16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 Ye s

TIMx

(TIM2,

TIM3,

TIM4,

TIM5)

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 N o

TIM6,

TIM7

16-bit Up

Any integer

between 1

and 65536

Ye s 0 N o

Description STM32F105xx, STM32F107xx

18/104 Doc ID 15274 Rev 6

Any of the standard timers can be used to generate PWM outputs. Each of the timers has

independent DMA request generations.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.16 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A

hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F105xx and STM32F107xx connectivity line embeds three universal

synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and

two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other

available interfaces communicate at up to 2.25 Mbit/s.

STM32F105xx, STM32F107xx Description

Doc ID 15274 Rev 6 19/104

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS

signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All

interfaces can be served by the DMA controller except for UART5.

2.3.18 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in

full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC/SDHC

(a)

modes.

All SPIs can be served by the DMA controller.

2.3.19 Inter-integrated sound (I

Two standard I

S interfaces (multiplexed with SPI2 and SPI3) are available, that can be

operated in master or slave mode. These interfaces can be configured to operate with 16/32

bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

96 kHz are supported. When either or both of the I

S interfaces is/are configured in master

mode, the master clock can be output to the external DAC/CODEC at 256 times the

sampling frequency with less than 0.5% accuracy error owing to the advanced clock

controller (see Section 2.3.7: Clocks and startup).

Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral

interface (SPI)” section of the STM32F10xxx reference manual.

2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard media-independent

interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx

requires an external physical interface device (PHY) to connect to the physical LAN bus

(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many

as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz

(RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

● Supports 10 and 100 Mbit/s rates

● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors (see the STM32F105xx/STM32F107xx reference manual for

details)

● Tagged MAC frame support (VLAN support)

● Half-duplex (CSMA/CD) and full-duplex operation

● MAC control sublayer (control frames) support

a. SDHC = Secure digital high capacity.

Description STM32F105xx, STM32F107xx

20/104 Doc ID 15274 Rev 6

● 32-bit CRC generation and removal

● Several address filtering modes for physical and multicast address (multicast and group

addresses)

● 32-bit status code for each transmitted or received frame

● Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive

FIFO are both 2 Kbytes, that is 4 Kbytes in total

● Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with

the timestamp comparator connected to the TIM2 trigger input

● Triggers interrupt when system time becomes greater than target time

2.3.21 Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to

1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)

are not shared with any other peripheral.

2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-

speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS

peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It

has software-configurable endpoint setting and supports suspend/resume. The USB OTG

full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL

connected to the HSE oscillator. The major features are:

● 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other

peripheral)

● 4 bidirectional endpoints

● HNP/SNP/IP inside (no need for any external resistor)

● for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

● the SOF output can be used to synchronize the external audio DAC clock in

isochronous mode

● in accordance with the USB 2.0 Specification, the supported transfer speeds are:

– in Host mode: full speed and low speed

– in Device mode: full speed

2.3.23 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

剩余102页未读，继续阅读

wzg471463175

粉丝: 0
资源: 10

STM32F107系列：全能ARM微控制器，集成丰富功能

STM32F107xxx微控制器掉电检测技术详解

STM32F107中文参考手册翻译版

STM32F107中文参考手册：技术详解与更新

STM32F107-1.rar_LXI stm32_STM32F107 PDF_nichelite for stm32_stm3

STM32F107xxx掉电检测

stm32f107用户手册

STM32F107用户手册（中文版）

使用stm32f107的RTC实现时钟和日期控制

STM32F107中文参考手册解析

STM32F107中文参考手册：技术解析与更新

最新资源