基于FPGA和Handel C实现SoC系统设计

FPGA

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List of Figures xix

6.1 Defining membership function for different seasons . . . . . . . . . . . . . . . 118

6.2 Membership function of water temperature . . . . . . . . . . . . . . . . . . . . . . 119

6.3 Design flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.4 RTL realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.5 Timing verification using the ModelSim . . . . . . . . . . . . . . . . . . . . . . . . 122

6.6 FSM model of the packet processor core . . . . . . . . . . . . . . . . . . . . . . . . 126

6.7 Simulation window of Packet Processor exhibiting

the Mixed Mode Flow with ANSI C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6.8 Simulation report using ModelSim, the timeline (yellow) is the

reference to validate the timing at a particular instance . . . . . . . . . . . . . 133

6.9 RTL view of the packet splitter using Xilinx Webpack . . . . . . . . . . . . . 134

6.10 RTL realization of the LCG core on Xilinx spartan III FPGA . . . . . . . . 135

6.11 RTL realization of the Blowfish Soft IP core . . . . . . . . . . . . . . . . . . . . . 137

7.1 Block diagram of the temperature control system application with

integration of Picoblaze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.2 PBlaze IDE interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.3 LUT based implementation of the temperature controller . . . . . . . . . . . 152

7.4 Block Schematic of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.5 RTL hierarchical version of the implementation . . . . . . . . . . . . . . . . . . 157

xxiii

List of Programs

3.1 Handel C code for D Flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2 Handel C code for realizing Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.3 Handel C code for JK Flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.4 Realizing cell of Hex Counter using Handel C. . . . . . . . . . . . . . . . . . . . . 50

3.5 Realization of Universal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.6 Handel C code for LFSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.7 Handel C code for frequency scalar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.8 Handel C code for FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.9 Handel C code for LIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.10 Handel C code for hamming code IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1 Handel C code for 2 to 4 Decoder IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.2 Handel C code for 3 to 8 Decoder IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3 Handel C code for 3 to 8 Decoder IP in non-hierarchical manner using

switch construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4 Handel C code for 4 to 2 priority encoder . . . . . . . . . . . . . . . . . . . . . . . . 67

4.5 Handel C code for 7 to 3 priority encoder . . . . . . . . . . . . . . . . . . . . . . . . 68

4.6 Handel C realization of 8 bit parity generator . . . . . . . . . . . . . . . . . . . . . 70

4.7 Handel C realization IP parity Checker . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.8 Handel C realization BCD to seven segment converter . . . . . . . . . . . . . . 73

4.9 Handel C code for binary to gary converter . . . . . . . . . . . . . . . . . . . . . . . 75

4.10 Handel C code for realization of IP core of gray to binary converter. . . . 77

4.11 Handel C code for barrel shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1 Handel C code for half adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.2 Handel C code for 8 bit full adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3 Handel C code for ripple carry adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.4 Handel C code for booth algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.5 Handel C code for 8 bit ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.6 Handel C code for adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.7 Handel C core as a black box In EDK . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1 Handel C code for fuzzy controller realization. . . . . . . . . . . . . . . . . . . . . 120

6.2 Handel C code for TCP/IP packet processor implementation . . . . . . . . . 126

6.3 Handel C code for LCG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

R.K. Kamat et al., Unleash the System on Chip using FPGAs and Handel C,

DOI 10.1007/978-1-4020-9362-3_1, © Springer Science+Business Media B.V. 2009

The electronics industry is an amazingly fast changing and vigorous environment,

driven by everlasting demand for innovation and technological advancement. As

electronic manufacturers need to develop affluent features that will set apart new

products, devices attain progressively more functions and head towards the com-

plexity beating the Moor’s law. These have resulted in narrow market windows

and accelerate obsolescence cycles that naturally impose reduced development

times.

State of art electronic devices requires chips that dwell in a small footprint, less

hungry interms of power, and fast enough to deal with the sophisticated applica-

tions. Traditionally, semiconductor devices were developed with a notion of single,

dedicated function. A system used to be analytical marriage of the subsystems for

the intended application. However, the new era is all about the complete systems on

a single chip. The state of the art systems have multiple processors or similar com-

plex functional blocks interacting with each-other and with the real world as well to

satisfy the needs of the appliance. In recent times SoC has emerged as the promising

solution to all the above mentioned requirements. Owing to their applicability in the

sophisticated systems, the SoC’s are finding their place mainly in computers, com-

munication equipment, consumer electronic devices, and automotive applications.

The Soc Market is fuelled by their growing demand in new consumer applications,

which include mobile phones, and automotives. Yet another factor that has escalated

the SoC demand is the growing digital convergence and the technological progress

towards the heterogeneous systems being placed on-chip. However the end result

faced by the designer community is tremendous pressure with the shrinking time-

to-market window. The complexity and heterogeneity of today’s SOCs has forced

the designers to devote more time for the simulation, verification and prototyping

aspects.

Like all electronic systems, System-on-Chip (SoC) are subject to the contradic-

tory trade-offs such as increase in complexity Vs decrease in time and costs. In addi-

tion, specific SoC characteristics aggravate difficulties in their design with growing

multidisciplinary applications, closer hardware software codesign issues, demand

for small footprint, custom Vs semicustom platforms to name a few.

Chapter 1

Introduction

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