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飞思卡尔QorIQ P2020处理器参考手册
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"MPC2020使用手册是针对飞思卡尔(Freescale)的QorIQ P2020集成处理器的一份参考手册,该手册同样适用于E500V2核,同时也可作为了解E500核的参考资料。手册发布于2009年7月,版本为Rev.0。"
MPC2020是基于Power Architecture技术的微处理器,由Freescale Semiconductor(现为NXP Semiconductors的一部分)设计。这个处理器系列,如P2020和P2010,主要应用于高性能、低功耗的嵌入式系统中。E500V2核是PowerPC架构的一种变体,它在效率和性能之间提供了良好的平衡,常见于各种工业和嵌入式应用。
手册详细介绍了P2020处理器的各项特性和功能,包括其核心架构、指令集、内存管理、中断处理、电源管理、以及外设接口等。E500V2核的设计特点可能包括多线程能力、超标量执行、动态电压和频率调整(DVFS),以及优化的能源效率。
在硬件层面,P2020处理器可能包含多个处理器核心、高速缓存系统、以及对多种通信协议的支持,如RapidIO(一种高性能串行互连技术)、PCI Express、以太网(遵循IEEE 802.3标准)等。此外,手册还会涵盖中断控制器、时钟管理、安全特性,如加密引擎,以及各种调试工具和接口的使用方法。
软件开发方面,手册会提供关于如何在P2020上进行操作系统移植、驱动程序编写、以及性能优化的指导。这通常涉及到对PowerPC汇编语言和C/C++编程的支持,以及对实时操作系统(RTOS)和嵌入式Linux的适应性。
值得注意的是,尽管手册提供了设计和实现Freescale Semiconductor产品的信息,但它并不授予任何版权许可来设计或制造集成电路。所有产品和服务名称均属于各自所有者的财产。
"MPC2020使用手册"对于那些需要深入了解和开发基于P2020或E500V2核系统的工程师来说,是一份非常宝贵的资源,它提供了全面的技术细节和实用指南,有助于系统和软件开发者充分利用这些处理器的潜力。
QorIQ P2020 Integrated Processor Reference Manual, Rev. 0
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
12.1.3.1 eLBC Bus Clock and Clock Ratios ....................................................................... 12-4
12.1.3.2 Source ID Debug Mode......................................................................................... 12-4
12.2 External Signal Descriptions ......................................................................................... 12-5
12.3 Memory Map/Register Definition ................................................................................. 12-9
12.3.1 Register Descriptions............................................................................................... 12-11
12.3.1.1 Base Registers (BR0–BR7) ................................................................................. 12-11
12.3.1.2 Option Registers (OR0–OR7).............................................................................. 12-13
12.3.1.2.1 Address Mask .................................................................................................. 12-14
12.3.1.2.2 Option Registers (ORn)—GPCM Mode .........................................................12-15
12.3.1.2.3 Option Registers (ORn)—FCM Mode ............................................................ 12-17
12.3.1.2.4 Option Registers (ORn)—UPM Mode............................................................ 12-20
12.3.1.3 UPM Memory Address Register (MAR)............................................................. 12-21
12.3.1.4 UPM Mode Registers (MxMR) ........................................................................... 12-22
12.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 12-24
12.3.1.6 UPM/FCM Data Register (MDR) ....................................................................... 12-24
12.3.1.7 Special Operation Initiation Register (LSOR).....................................................12-25
12.3.1.8 UPM Refresh Timer (LURT)............................................................................... 12-26
12.3.1.9 Transfer Error Status Register (LTESR).............................................................. 12-27
12.3.1.10 Transfer Error Check Disable Register (LTEDR)................................................ 12-29
12.3.1.11 Transfer Error Interrupt Enable Register (LTEIR) .............................................. 12-30
12.3.1.12 Transfer Error Attributes Register (LTEATR)..................................................... 12-31
12.3.1.13 Transfer Error Address Register (LTEAR).......................................................... 12-32
12.3.1.14 Transfer Error ECC Register (LTECCR)............................................................. 12-32
12.3.1.15 Local Bus Configuration Register (LBCR)......................................................... 12-33
12.3.1.16 Clock Ratio Register (LCRR).............................................................................. 12-35
12.3.1.17 Flash Mode Register (FMR)................................................................................ 12-36
12.3.1.18 Flash Instruction Register (FIR).......................................................................... 12-38
12.3.1.19 Flash Command Register (FCR) ......................................................................... 12-39
12.3.1.20 Flash Block Address Register (FBAR)................................................................ 12-40
12.3.1.21 Flash Page Address Register (FPAR) .................................................................. 12-40
12.3.1.22 Flash Byte Count Register (FBCR)..................................................................... 12-42
12.3.1.23 Flash ECC Blockn Register (FECC0–FECC3) ................................................... 12-42
12.4 Functional Description................................................................................................. 12-43
12.4.1 Basic Architecture.................................................................................................... 12-44
12.4.1.1 Address and Address Space Checking ................................................................ 12-44
12.4.1.2 External Address Latch Enable Signal (LALE) .................................................. 12-44
12.4.1.3 Data Transfer Acknowledge (TA) ....................................................................... 12-46
12.4.1.4 Data Buffer Control (LBCTL)............................................................................. 12-47
12.4.1.5 Atomic Operation ................................................................................................ 12-47
12.4.1.6 Parity Generation and Checking (LDP)............................................................... 12-48
12.4.1.7 Bus Monitor......................................................................................................... 12-48
QorIQ P2020 Integrated Processor Reference Manual, Rev. 0
Freescale Semiconductor xvii
Contents
Paragraph
Number Title
Page
Number
12.4.1.8 PLL Bypass Mode ............................................................................................... 12-48
12.4.2 General-Purpose Chip-Select Machine (GPCM).....................................................12-49
12.4.2.1 GPCM Read Signal Timing................................................................................. 12-50
12.4.2.2 GPCM Write Signal Timing................................................................................ 12-52
12.4.2.3 Chip-Select Assertion Timing ............................................................................. 12-54
12.4.2.3.1 Programmable Wait State Configuration......................................................... 12-54
12.4.2.3.2 Chip-Select and Write Enable Negation Timing .............................................12-55
12.4.2.3.3 Relaxed Timing ............................................................................................... 12-55
12.4.2.3.4 Output Enable (LOE) Timing.......................................................................... 12-58
12.4.2.3.5 Extended Hold Time on Read Accesses.......................................................... 12-58
12.4.2.4 External Access Termination (LGTA) ................................................................. 12-60
12.4.2.5 GPCM Boot Chip-Select Operation .................................................................... 12-60
12.4.3 Flash Control Machine (FCM) ................................................................................ 12-61
12.4.3.1 FCM Buffer RAM ............................................................................................... 12-63
12.4.3.1.1 Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 12-64
12.4.3.1.2 Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 12-65
12.4.3.1.3 Error Correcting Codes and the Spare Region ................................................ 12-66
12.4.3.2 Programming FCM.............................................................................................. 12-68
12.4.3.2.1 FCM Command Instructions ........................................................................... 12-69
12.4.3.2.2 FCM No-Operation Instruction ....................................................................... 12-69
12.4.3.2.3 FCM Address Instructions............................................................................... 12-69
12.4.3.2.4 FCM Data Read Instructions ........................................................................... 12-70
12.4.3.2.5 FCM Data Write Instructions .......................................................................... 12-70
12.4.3.3 FCM Signal Timing ............................................................................................. 12-71
12.4.3.3.1 FCM Chip-Select Timing ................................................................................ 12-71
12.4.3.3.2 FCM Command, Address, and Write Data Timing .........................................12-71
12.4.3.3.3 FCM Ready/Busy Timing................................................................................ 12-73
12.4.3.3.4 FCM Read Data Timing .................................................................................. 12-73
12.4.3.3.5 FCM Extended Read Hold Timing.................................................................. 12-74
12.4.3.4 FCM Boot Chip-Select Operation ....................................................................... 12-75
12.4.3.4.1 FCM Bank 0 Reset Initialization..................................................................... 12-75
12.4.3.4.2 Boot Block Loading into the FCM Buffer RAM............................................. 12-76
12.4.4 User-Programmable Machines (UPMs)................................................................... 12-78
12.4.4.1 UPM Requests ..................................................................................................... 12-79
12.4.4.1.1 Memory Access Requests................................................................................ 12-80
12.4.4.1.2 UPM Refresh Timer Requests ......................................................................... 12-80
12.4.4.1.3 Software Requests—RUN Command ............................................................. 12-80
12.4.4.1.4 Exception Requests.......................................................................................... 12-81
12.4.4.2 Programming the UPMs ...................................................................................... 12-81
12.4.4.2.1 UPM Programming Example (Two Sequential Writes to the RAM Array).... 12-82
12.4.4.2.2 UPM Programming Example (Two Sequential Reads from the RAM Array) 12-82
QorIQ P2020 Integrated Processor Reference Manual, Rev. 0
xviii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
12.4.4.3 UPM Signal Timing............................................................................................. 12-83
12.4.4.4 RAM Array.......................................................................................................... 12-83
12.4.4.4.1 RAM Words..................................................................................................... 12-84
12.4.4.4.2 Chip-Select Signal Timing (CSTn) ................................................................. 12-87
12.4.4.4.3 Byte Select Signal Timing (BSTn).................................................................. 12-88
12.4.4.4.4 General-Purpose Signals (GnTn, GOn)........................................................... 12-88
12.4.4.4.5 Loop Control (LOOP) ..................................................................................... 12-88
12.4.4.4.6 Repeat Execution of Current RAM Word (REDO).........................................12-89
12.4.4.4.7 Address Multiplexing (AMX) ......................................................................... 12-89
12.4.4.4.8 Data Valid and Data Sample Control (UTA) ................................................... 12-91
12.4.4.4.9 LGPL[0:5] Signal Negation (LAST)............................................................... 12-91
12.4.4.4.10 Wait Mechanism (WAEN)............................................................................... 12-91
12.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 12-92
12.4.4.6 Extended Hold Time on Read Accesses.............................................................. 12-93
12.5 Initialization/Application Information......................................................................... 12-93
12.5.1 Interfacing to Peripherals in Different Address Modes........................................... 12-93
12.5.1.1 Multiplexed Address/Data Bus for 32-Bit Addressing........................................ 12-93
12.5.1.2 Non-Multiplexed Address and Data Buses.......................................................... 12-94
12.5.1.3 Peripheral Hierarchy on the Local Bus for High Bus Speeds ............................. 12-94
12.5.1.4 GPCM Timings.................................................................................................... 12-95
12.5.2 Bus Turnaround ....................................................................................................... 12-96
12.5.2.1 Address Phase after Previous Read ..................................................................... 12-96
12.5.2.2 Read Data Phase after Address Phase ................................................................. 12-96
12.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks......................... 12-97
12.5.2.4 UPM Cycles with Additional Address Phases.....................................................12-97
12.5.3 Interface to Different Port-Size Devices.................................................................. 12-97
12.5.4 Command Sequence Examples for NAND Flash EEPROM...................................12-98
12.5.4.1 NAND Flash Soft Reset Command Sequence Example ..................................... 12-99
12.5.4.2 NAND Flash Read Status Command Sequence Example...................................12-99
12.5.4.3 NAND Flash Read Identification Command Sequence Example....................... 12-99
12.5.4.4 NAND Flash Page Read Command Sequence Example................................... 12-100
12.5.4.5 NAND Flash Block Erase Command Sequence Example ................................ 12-101
12.5.4.6 NAND Flash Program Command Sequence Example...................................... 12-101
12.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ............................................. 12-102
12.5.6 Interfacing to ZBT SRAM Using UPM................................................................. 12-107
Chapter 13
DMA Controller
13.1 Introduction.................................................................................................................... 13-1
13.1.1 Block Diagram........................................................................................................... 13-1
QorIQ P2020 Integrated Processor Reference Manual, Rev. 0
Freescale Semiconductor xix
Contents
Paragraph
Number Title
Page
Number
13.1.2 Overview....................................................................................................................13-2
13.1.3 Features......................................................................................................................13-2
13.1.4 Modes of Operation ................................................................................................... 13-2
13.2 External Signal Description........................................................................................... 13-5
13.2.1 Signal Overview ........................................................................................................ 13-5
13.2.2 Detailed Signal Descriptions ..................................................................................... 13-5
13.3 Memory Map/Register Definition ................................................................................. 13-6
13.3.1 DMA Register Descriptions....................................................................................... 13-9
13.3.1.1 Mode Registers (MRn).......................................................................................... 13-9
13.3.1.2 Status Registers (SRn) ......................................................................................... 13-12
13.3.1.3 Current Link Descriptor Address Registers (CLNDARn and ECLNDARn)...... 13-13
13.3.1.4 Source Attributes Registers (SATRn).................................................................. 13-15
13.3.1.5 Source Address Registers (SARn)....................................................................... 13-16
13.3.1.5.1 Source Address Registers for RapidIO Maintenance Reads
(SARn)......................................................................................................... 13-17
13.3.1.6 Destination Attributes Registers (DATRn).......................................................... 13-17
13.3.1.7 Destination Address Registers (DARn)............................................................... 13-18
13.3.1.7.1 Destination Address Registers for RapidIO Maintenance Writes
(DARn)........................................................................................................ 13-19
13.3.1.8 Byte Count Registers (BCRn) ............................................................................. 13-20
13.3.1.9 Next Link Descriptor Address Registers (NLNDARn and ENLNDARn).......... 13-20
13.3.1.10 Current List Descriptor Address Registers (CLSDARn and ECLSDARn)......... 13-21
13.3.1.11 Next List Descriptor Address Registers (NLSDARn and ENLSDARn)............. 13-23
13.3.1.12 Source Stride Registers (SSRn) ........................................................................... 13-24
13.3.1.13 Destination Stride Registers (DSRn) ................................................................... 13-24
13.3.1.14 DMA General Status Register (DGSR)............................................................... 13-25
13.4 Functional Description................................................................................................. 13-27
13.4.1 DMA Channel Operation......................................................................................... 13-27
13.4.1.1 Basic DMA Mode Transfer ................................................................................. 13-28
13.4.1.1.1 Basic Direct Mode........................................................................................... 13-28
13.4.1.1.2 Basic Direct Single-Write Start Mode ............................................................. 13-28
13.4.1.1.3 Basic Chaining Mode ...................................................................................... 13-29
13.4.1.1.4 Basic Chaining Single-Write Start Mode ........................................................ 13-29
13.4.1.2 Extended DMA Mode Transfer ........................................................................... 13-30
13.4.1.2.1 Extended Direct Mode..................................................................................... 13-30
13.4.1.2.2 Extended Direct Single-Write Start Mode....................................................... 13-30
13.4.1.2.3 Extended Chaining Mode ................................................................................ 13-30
13.4.1.2.4 Extended Chaining Single-Write Start Mode .................................................. 13-31
13.4.1.3 External Control Mode Transfer.......................................................................... 13-31
13.4.1.4 Channel Continue Mode for Cascading Transfer Chains .................................... 13-32
13.4.1.4.1 Basic Mode...................................................................................................... 13-33
QorIQ P2020 Integrated Processor Reference Manual, Rev. 0
xx Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
13.4.1.4.2 Extended Mode................................................................................................ 13-33
13.4.1.5 Channel Abort...................................................................................................... 13-33
13.4.1.6 Bandwidth Control............................................................................................... 13-33
13.4.1.7 Channel State....................................................................................................... 13-34
13.4.1.8 Illustration of Stride Size and Stride Distance..................................................... 13-34
13.4.2 DMA Transfer Interfaces......................................................................................... 13-35
13.4.3 DMA Errors ............................................................................................................. 13-35
13.4.4 DMA Descriptors..................................................................................................... 13-35
13.4.5 Limitations and Restrictions.................................................................................... 13-38
13.5 DMA System Considerations ...................................................................................... 13-40
13.5.1 Unusual DMA Scenarios ......................................................................................... 13-41
13.5.1.1 DMA to e500 Core .............................................................................................. 13-41
13.5.1.2 DMA to Configuration, Control, and Status Registers........................................ 13-42
13.5.1.3 DMA to I
2
C ......................................................................................................... 13-42
13.5.1.4 DMA to DUART ................................................................................................. 13-42
Chapter 14
Enhanced Three-Speed Ethernet Controllers
14.1 Overview........................................................................................................................14-1
14.2 Features..........................................................................................................................14-2
14.3 Modes of Operation ....................................................................................................... 14-5
14.4 External Signals Description ......................................................................................... 14-6
14.4.1 Detailed Signal Descriptions ..................................................................................... 14-9
14.5 Memory Map/Register Definition ............................................................................... 14-14
14.5.1 Top-Level Module Memory Map ............................................................................ 14-15
14.5.2 Detailed Memory Map............................................................................................. 14-15
14.5.3 Memory-Mapped Register Descriptions.................................................................. 14-26
14.5.3.1 eTSEC General Control and Status Registers...................................................... 14-26
14.5.3.1.1 Controller ID Register (TSEC_ID).................................................................. 14-26
14.5.3.1.2 Controller ID Register (TSEC_ID2)................................................................ 14-27
14.5.3.1.3 Interrupt Event Register (IEVENT) ................................................................ 14-28
14.5.3.1.4 Interrupt Mask Register (IMASK) .................................................................. 14-31
14.5.3.1.5 Error Disabled Register (EDIS)....................................................................... 14-33
14.5.3.1.6 Ethernet Control Register (ECNTRL)............................................................. 14-35
14.5.3.1.7 Pause Time Value Register (PTV) ................................................................... 14-37
14.5.3.1.8 DMA Control Register (DMACTRL) ............................................................. 14-38
14.5.3.1.9 TBI Physical Address Register (TBIPA)......................................................... 14-40
14.5.3.2 eTSEC Transmit Control and Status Registers.................................................... 14-40
14.5.3.2.1 Transmit Control Register (TCTRL) ............................................................... 14-40
14.5.3.2.2 Transmit Status Register (TSTAT)................................................................... 14-42
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