2020.1版UG1262 Model Composer MATLAB集成指南

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UG1262 "Model Composer 用户指南" 是一份针对Xilinx Vivado工具的详细文档，专注于基于模型的开发过程，特别是在设计和实现数字信号处理(DSP)算法时的使用。这份文档适用于Vivado 2020.1版本，更新了C++代码生成的相关部分，以便开发者能够更好地利用Model Composer与MATLAB集成。该用户指南强调了以下几个关键知识点： 1. **MATLAB支持**： Model Composer 支持多个MATLAB版本，包括2019a、2019b和2020a，这对于设计师来说是重要的选择，因为不同的MATLAB版本可能提供不同的功能和性能优化。在使用时，请确保选用与Model Composer兼容的MATLAB版本。 2. **操作系统兼容性**： - 对于x86和x86-64架构的系统，推荐的操作系统包括： - Microsoft Windows 10 (1809、1903、1909 更新，64位) - Red Hat Enterprise Workstation/Server (7.4、7.5、7.6、7.7，64位) - Ubuntu Linux (16.04.5 LTS 至 18.04.4 LTS，64位) 特别指出的是，MATLAB R2020a版本不支持Red Hat Enterprise Linux 7.4。 3. **文档结构**：用户指南包含了详细的章节，如"Chapter 1: Introduction"，这可能会涉及Model Composer的基础知识，如安装、界面介绍以及如何设置工作环境。后续章节可能会探讨如何使用Model Composer创建、修改和验证模型，以及将模型转换为硬件可执行代码的过程。 4. **代码生成**：文档强调了C++代码的生成，这是Model Composer的重要功能之一，它允许用户将MATLAB模型转换成可以在Xilinx FPGA或SoC上运行的高性能代码。这个过程可能包括模型编译、配置和部署步骤。 5. **反馈机制**：提供了发送反馈的途径，意味着用户可以向Xilinx报告遇到的问题，分享经验，或者提出改进建议，以便持续优化和改进Model Composer的功能和用户体验。 UG1262 "Model Composer 用户指南" 是一个宝贵的资源，对于从事基于MATLAB的FPGA或SoC DSP算法设计的工程师而言，它提供了全面的指导，涵盖了从软件模型设计到硬件实现的全流程。阅读和理解这份文档有助于提升开发效率和产品质量。

You can connect into an exisng line by right-clicking and dragging the mouse. This creates a

branching line connected to the exisng signal line at the specied locaon. The branch line can

connect to an input or output as appropriate to the connected signal.

TIP: You can also connect blocks by selecng them sequenally while holding the Ctrl key. This connects the

output of the rst block into the input of the second block. Keeping the Ctrl key pressed and selecng another

block connues the connecon chain.

Simulink updates the model when you Run simulaon. You can also update the model using the

Simulaon → Update Diagram menu command, or by typing Ctrl+D at any point in the design

process. You will see the Data Types, Signal Dimensions and Sample Times from the source

blocks propagate through the model.

TIP: You can use the Display → Signals and Ports menu command to enable the various data that you want

displayed in your model, such as Signal Dimensions and Port Data Types.

You cannot specify sample mes on Model Composer blocks, except for the Constant block from

the Source library of the Xilinx Model Composer block library. Model Composer infers the sample

me from the source blocks connected at the input of the model, and does not support mulple

sample mes in the Model Composer design.

By updang the diagram from me to me, you can see and x potenal design issues as you

develop the model. This approach can make it easier to idenfy the sources of problems by

liming the scope to recent updates to the design. The Update Diagram is also faster than

running simulaon.

Working with Data Types

Data types supported by Model Composer include the following:

Table 2: Model Composer Data Types

Name Description

double Double-precision floating point

single Single-precision floating point

half

Half-precision floating point

int8 Signed 8-bit integer

uint8 Unsigned 8-bit integer

int16 Signed 16-bit integer

uint16 Unsigned 16-bit integer

int32 Signed 32-bit integer

uint32 Unsigned 32-bit integer

fixed

Signed and unsigned fixed point

Chapter 2: Creating a Model Composer Design

UG1262 (v2020.1) June 3, 2020 www.xilinx.com

Model Composer User Guide 16

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1. Convert Xilinx Model Composer xed-point data type to the double data type using the

DTC block from the Xilinx Model Composer library in the Library Browser.

2. Convert the double data type to Simulink format xed-point data type using the Simulink

Data Type Conversion block from the Simulink Signal Aributes library in the Library

Browser.

3. Match the signedness, word length, and fraconal length between the two xed-point data

types.

TIP: Converng between the Xilinx Model Composer xed data type and the Simulink xed data type is not

recommended unless necessary for your design. You can convert from the Model Composer xed-point data

type to double, as shown in the rst step, and this should be sucient for most applicaons.

Although handling xed-point data type in a design is more me consuming, the value of using

xed-point data types for applicaons targeted at implementaon in an FPGA is worth the

challenge. It is widely accepted that designing in oang point leads to higher power usage for

the design. This is true for FPGAs where oang-point DSP blocks have been hardened onto the

FPGA and users must implement a oang point soluon using DSP blocks and addional device

resources. Floang-point implementaons require more FPGA resources than an equivalent

xed-point soluon. With this higher resource usage comes higher power consumpon and

ulmately increased overall cost of implemenng the design. For more informaon refer to the

white paper Reduce Power and Cost by Converng from Floang Point to Fixed Point (WP491).

Working with Half Data Types

Xilinx Model Composer also supports a half precision oang point data type, which is 16 bits

wide instead of 32 bits, because it consumes less real estate on the target device when

implemented on the FPGA. This is an important consideraon when designing in Model

Composer. However, Simulink does not support the half data type, and this can lead to errors in

simulaon. The soluon is to use the Model Composer DTC block to convert the half into the

single data type supported by Simulink, for those porons of the design that are not in the

Model Composer sub-module and will not be part of the generated output.

Working with Data Type Expression

Model Composer lets you specify data types as an expression. Currently the following Model

Composer library blocks support data type expression:

• Constant

• Data Type Conversion

• Gain

• Look-Up Table

• Reinterpret

Chapter 2: Creating a Model Composer Design

UG1262 (v2020.1) June 3, 2020 www.xilinx.com

Model Composer User Guide 20

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