MIPS32指令集手册V6.06：详细描述与指南

需积分: 12 196 浏览量更新于2024-07-16 收藏 6.23MB PDF 举报

MD00086-2B-MIPS32BIS-AFP-6.06是MIPS32指令集的手册，修订于2016年12月15日，旨在为程序员提供详细的MIPS32架构指导。该文档是专有的，可能会随时更新且无任何保证。手册包括丰富的内容，如排版约定、术语解释、伪代码符号、指令字段说明以及如何理解指令集。在手册的第1章中，作者介绍了手册的结构和使用指南。1.1节列出了三种不同的文本风格：斜体用于表示特定术语，粗体强调重要信息，而等宽字体用于显示代码或示例。UNPREDICTABLE、UNDEFINED和UNSTABLE这些术语用来描述指令行为，UNPREDICTABLE表示结果不可预测，UNDEFINED表示操作可能导致未定义的行为，而UNSTABLE则可能由于技术限制而不稳定。1.3节解释了伪代码中的特殊符号，1.4节则定义了如何表示寄存器字段的访问权限，以便于读者理解指令的执行细节。第2章“指令集指南”是手册的核心部分，它深入剖析了指令的组成和功能。2.1节讲解了指令字段的构成，包括指令描述名称、助记符、格式、目的、描述、限制、可用性和兼容性等。这些字段提供了对每个指令操作的全面理解，包括它执行的操作类型和可能的限制条件。例如，操作字段（Operation Field）详细说明了指令的具体功能，如算术运算、逻辑运算、数据传输等。此外，手册还强调了阅读时应关注的章节，如第2章中的格式、目的和描述字段，这些对于正确理解和编写符合MIPS32指令集规范的程序至关重要。整个手册的目标是帮助程序员高效利用MIPS32指令集，提高代码的可读性、效率和兼容性。 MD00086-2B-MIPS32BIS-AFP-6.06是一本详尽的MIPS32指令集参考文献，它涵盖了指令格式、含义、限制及使用的最佳实践，是编程人员在开发基于MIPS32架构的应用程序时不可或缺的参考资料。通过深入理解其中的知识点，开发者可以优化代码性能，确保软件的正确性和可维护性。

1.3 Special Symbols in Pseudocode Notation

The MIPS32® Instruction Set Manual, Revision 6.06 6

CPR[z,x,s] Coprocessor unit z, general register x, select s

CP2CPR[x] Coprocessor unit 2, general register x

CCR[z,x] Coprocessor unit z, control register x

CP2CCR[x] Coprocessor unit 2, control register x

COC[z] Coprocessor unit z condition signal

Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number

BigEndianMem Endian mode as configured at chip reset (0  Little-Endian, 1  Big-Endian). Specifies the endianness of

the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions) and the endi-

anness of Kernel and Supervisor mode execution.

BigEndianCPU The endianness for load and store instructions (0  Little-Endian, 1  Big-Endian). In User mode, this

endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com-

puted as (BigEndianMem XOR ReverseEndian).

ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only,

and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as

(SR

and User mode).

LLbit Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is

set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation,

when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc-

tions.

I:,

I+n:,

I-n:

This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction

time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current

instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a

time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the

instruction time of another instruction. When this happens, the instruction operation is written in sections

labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode

appears to occur. For example, an instruction may have a result that is not available until after the next

instruction. Such an instruction has the portion of the instruction operation description that writes the result

The effect of pseudocode statements for the current instruction labeled I+1 appears to occur “at the same

time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode

sequence, the effects of the statements take place in order. However, between sequences of statements for

different instructions that occur “at the same time,” there is no defined order. Programs must not depend on a

particular order of evaluation between such sections.

PC The Program Counter value. During the instruction time of an instruction, this is the address of the instruc-

tion word. The address of the instruction that occurs during the next instruction time is determined by assign-

ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any

pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc-

tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the

instruction time of the instruction in the branch delay slot.

In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the restart

address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an

exception. Release 6 adds PC-relative address computation and load instructions. The PC value contains a

full 32-bit address, all of which are signif

icant during a memory referen

ce.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

About This Book

7 The MIPS32® Instruction Set Manual, Revision 6.06

1.4 Notation for Register Field Accessibility

In this document, the read/write properties of register fields use the notations shown in Table 1.1.

ISA Mode In processors that implement the MIPS16e Application Specific Extension or the microMIPS base architec-

tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol-

lows:

In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a

combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link

instruction, or into a Coprocessor 0 register on an exception.

PABITS The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 phys-

ical address bits were implemented, the size of the physical address space would be 2

PABITS

= 2

bytes.

FP32RegistersMode Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). In MIPS32 Release 1, the FPU

has 32, 32-bit FPRs, in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and

optionally in MIPS32 Release2 and Release 3) the FPU has 32 64-bit FPRs in which 64-bit data types are

stored in any FPR.

In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a

compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In

such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro-

cessor operates as if it had 32, 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.

The value of FP32RegistersMode is computed from the FR bit in the Status register.

InstructionInBranchDe-

laySlot

Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch

or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is

false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which

is not executed in the delay slot of a branch or jump.

SignalException(excep-

tion, argument)

Causes an exception to be signaled, using the exception parameter as the type of exception and the argument

parameter as an exception-specific argument). Control does not return from this pseudocode function—the

exception is signaled at the point of the call.

Table 1.2 Read/Write Register Field Notation

Read/Write

Notation Hardware Interpretation Software Interpretation

R/W A field in which all bits are readable and writable by software and, potentially, by hardware.

Hardware updates of this field are visible by software read. Software updates of this field are visible by

hardware read.

If the Reset State of this field is ‘‘Undefined’’, either software or hardware must initialize the value before

the first read will return a predictable value. This should not be confused with the formal definition of

UNDEFINED behavior.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

Encoding Meaning

0 The processor is executing 32-bit MIPS instructions

1 The processor is executing MIIPS16e or microMIPS

instructions

1.4 Notation for Register Field Accessibility

The MIPS32® Instruction Set Manual, Revision 6.06 8

R A field which is either static or is updated only by

hardware.

If the Reset State of this field is either ‘‘0’’, ‘‘Pre-

set’’, or ‘‘Externally Set’’, hardware initializes this

field to zero or to the appropriate state, respectively,

on powerup. The term ‘‘Preset’’ is used to suggest

that the processor establishes the appropriate state,

whereas the term ‘‘Externally Set’’ is used to sug-

gest that the state is established via an external

source (e.g., personality pins or initialization bit

stream). These terms are suggestions only, and are

not intended to act as a requirement on the imple-

mentation.

If the Reset State of this field is ‘‘Undefined’’, hard-

ware updates this field only under those conditions

specified in the description of the field.

A field to which the value written by software is

ignored by hardware. Software may write any value

to this field without affecting hardware behavior.

Software reads of this field return the last value

updated by hardware.

If the Reset State of this field is ‘‘Undefined’’, soft-

ware reads of this field result in an UNPREDICT-

ABLE value except after a hardware update done

under the conditions specified in the description of

the field.

R0 R0 = reserved, read as zero, ignore writes by soft-

ware.

Hardware ignores software writes to an R0 field.

Neither the occurrence of such writes, nor the val-

ues written, affects hardware behavior.

Hardware always returns 0 to software reads of R0

fields.

The Reset State of an R0 field must always be 0.

If software performs an mtc0 instruction which

writes a non-zero value to an R0 field, the write to

the R0 field will be ignored, but permitted writes to

other fields in the register will not be affected.

Architectural Compatibility: R0 fields are reserved,

and may be used for not-yet-defined purposes in

future revisions of the architecture.

When writing an R0 field, current software should

only write either all 0s, or, preferably, write back the

same value that was read from the field.

Current software should not assume that the value

read from R0 fields is zero, because this may not be

true on future hardware.

Future revisions of the architecture may redefine an

R0 field, but must do so in such a way that software

which is unaware of the new definition and either

writes zeros or writes back the value it has read from

the field will continue to work correctly.

Writing back the same value that was read is guaran-

teed to have no unexpected effects on current or

future hardware behavior. (Except for non-atomicity

of such read-writes.)

Writing zeros to an R0 field may not be preferred

because in the future this may interfere with the oper-

ation of other software which has been updated for

the new field definition.

Table 1.2 Read/Write Register Field Notation (Continued)

Read/Write

Notation Hardware Interpretation Software Interpretation

剩余484页未读，继续阅读

sti_tch

粉丝: 0
资源: 1

MIPS32指令集手册V6.06：详细描述与指南

busybox-1.31.1-mips

samba-3.0.37-mips32r1-linux-static.tar.xz

BCM5461S芯片资料

MD00582-2B-microMIPS32-AFP-6.05_MIPS32官方指令集_MIPS_源码.zip

MD00582-2B-microMIPS32-AFP-6.05_MIPS32官方指令集_MIPS_

PN00116-06.61-2B-MIPSSW-MSDE-v6.06.01.tgz，安装包

MD00672-2B-M14Kc-DTS-02.05.pdf

[龙芯.MIPS.汇编.自学.教程].-.MIPS.Assembly.Tutorial.eBook

Linux-armv7-arm64-mips32-strace.bin

3(5)-CPU子系统-MIPS-1-MIPS32指令架构与指令集1

最新资源