DDR3 DFI 2.1接口规范详解：信号、时序与功能全面解读

需积分: 45 148 浏览量更新于2024-07-15 收藏 909KB PDF 举报

DDRPHY-Interface-Specification-v2.1.pdf是一份详细描述DDR3 (Double Data Rate Three) Dynamic Frequency Interface (DFI) 第2.1版的规格文档。DFI是一种在DDR3内存系统中连接控制器（如CPU或南桥）和内存PHY（物理层接口）的标准接口规范，旨在确保高速数据传输的可靠性和一致性。这份标准提供了关于信号名称、时序特征以及功能的深入理解，对于设计和实现DDR3内存系统至关重要。 DFI 2.1版本包含了以下几个关键内容： 1. 信号定义：文档详尽地列出了DFI 2.1中使用的各种信号，包括命令、地址、数据、时钟、控制信号等，这些信号用于管理内存读写操作，以及调整工作频率和时序。 2. 时序参数：规范中包含了严格的时序规定，如信号上升沿、下降沿时间、setup时间和hold时间等，这些时序参数确保了数据在接口上的正确传输，防止数据损坏和延迟。 3. 功能特性：DFI 2.1着重于DDR3特有的功能，如读写级别控制，它允许控制器更精确地管理数据读取和写入操作，以优化性能和电源效率。此外，还包括了关于PHY评估模式和栅极训练特定模式信号的更新，这有助于提高系统的兼容性和稳定性。 4. 版本更新历史：文档还列出了从1.0到2.1版本的主要变更，展示了标准的迭代过程，以及针对DDR3技术的具体修改，反映了业界对内存速度和容量不断提升的需求。 5. 版权与支持：Denali Software, Inc.是该规范的主要发布者，提供技术支持、销售信息以及访问公司网站获取更多资源的途径。 DDRPHY-Interface-Specification-v2.1.pdf文档为开发人员提供了一套全面的指南，帮助他们设计和实现高效、兼容的DDR3内存系统，并且对于理解和优化现代计算机架构中的内存子系统具有核心参考价值。通过遵循这个标准，工程师可以确保他们的硬件设计满足DDR3规范，从而达到最佳性能和稳定性。

Interface Signal Groups

16 of 100 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

More information on the write data interface is provided in Section 4.3, “Write

Transactions”. The signals and parameter in the write data interface are listed in Table 4

and Table 5.

TABLE 4. Write Data Signals

Signal From Width Default Description

dfi_wrdata

or dfi_wrdata_pN

MC DFI Data

Width

a. This signal is not meaningful during initialization. Therefore, no default value is required to be maintained for this signal.

Write data bus. The write data stream must begin t

phy_wrdata

cycles

after the dfi_wrdata_en signal is asserted for the number of cycles

that the dfi_wrdata_en signal is asserted.

For frequency ratio systems, the write data bus will be replicated

into phase-specific dfi_wrdata_pN buses that define the write data

for each phase N of the PHY clock.

dfi_wrdata_en

or dfi_wrdata_en_pN

MC DFI Data

Enable

Width

b. Since all bits of the dfi_wrdata_en signal are identical, the width of the signal on the MC side and the PHY side may be

different; the PHY is not required to use all of the bits.

0x0 Write data and data mask enable. These signals must be asserted

phy_wrdata

cycles before the data and data mask are sent on the

DFI interface. The dfi_wrdata_en signal must be sent t

phy_wrlat

cycles after the write command.

Once the dfi_wrdata_en signal is asserted, it must remain asserted

for the number of contiguous cycles of write data passed through

the DFI write data interface.

The width of the dfi_wrdata_en signal is defined as a DFI term.

Ideally, there will be a single dfi_wrdata_en bit for each slice of

memory data. The dfi_wrdata_en [0] signal corresponds with the

lowest segment of dfi_wrdata signals.

For frequency ratio systems, the write data enable signals will be

replicated into phase-specific dfi_wrdata_en_pN signals that

define the validity of write data for each phase N of the PHY clock.

dfi_wrdata_mask

or dfi_wrdata_mask_pN

MC DFI Data

Width / 8

Write data byte mask. The timing is the same as for the dfi_wrdata

bus. The dfi_wrdata_mask [0] signal defines masking for the

dfi_wrdata [7:0] signals, the dfi_wrdata_mask [1] signal defines

masking for the dfi_wrdata [15:8] signals, etc. If the dfi_wrdata

bus is not a multiple of 8, then the uppermost bit of the

dfi_wrdata_mask signal corresponds to the most significant

partial byte of data.

For frequency ratio systems, the write data mask bus will be

replicated into phase-specific dfi_wrdata_mask_pN buses that

define the write data masking information for each phase N of the

PHY clock.

Interface Signal Groups

Denali Software DDR PHY Interface (DFI) Specification, Version 2.1 17 of 100

Denali Software, Inc.

3.3 Read Data Interface

The read data interface handles the return of read data across the DFI. The read

mechanism defined by the DFI includes signal definitions along with timing

relationships defined by DFI timing parameters. The signals dfi_rddata,

dfi_rddata_en, dfi_rddata_valid, the LPDDR2 signal dfi_rddata_dnv, along with the

related timing parameters t

rddata_en

and t

phy_rdlat

are described in Table 6 and Table 7.

The dfi_rddata_en signal is asserted t

rddata_en

cycles after a read command is asserted

on the DFI control interface and must remain asserted for the number of contiguous

cycles that read data is expected. One continuous assertion of the dfi_rddata_en signal

may encompass data for multiple read commands. The dfi_rddata_en signal de-asserts

to signify there is no more contiguous data expected from the DFI read command(s).

Note that the dfi_rddata_en signal is not required to be asserted for any fixed number

of cycles.

TABLE 5. Write Data Timing Parameters

Parameter

Defined

By Min Max Unit Description

phy_wrdata

PHY 0

a. The DFI does not specify a maximum value. The range of values supported is implementation-specific.

DFI PHY

clock

cycles

b. This timing parameter is defined in terms of DFI PHY clock cycles for frequency ratio systems. For matched frequency

systems, a DFI PHY clock is identical to the DFI clock.

Specifies the number of DFI PHY clock cycles between when the

dfi_wrdata_en signal is asserted to when the associated write data is

driven on the dfi_wrdata signal. This has no impact on performance,

only adjusts the relative time between enable and data transfer. DFI

1.0 and DFI 2.0 memory controllers will only support a t

phy_wrdata

value of 1. A PHY will generally be designed to operate at a single

phy_wrdata

value; however, the MC should support a range of values.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

phy_wrdelay

PHY 0

1 or 3

c. The PHY must support a maximum write data delay of one less than the clock ratio. A 1:2 frequency ratio PHY must support

values of 0 and 1. A 1:4 frequency ratio PHY must support a range of 0-3.

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles of additional delay

that the PHY must insert between the write data enable and write

data once data has been captured from the DFI bus. This parameter is

only used in frequency ratio systems.

phy_wrlat

PHY 0

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles between when a write

command is sent on the DFI control interface and when the

dfi_wrdata_en signal is asserted.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

Interface Signal Groups

18 of 100 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

The t

rddata_en

parameter defines the timing requirements between the read command on

the DFI interface and the assertion of the dfi_rddata_en signal at the DFI boundary for

the start of contiguous read data expected on the DFI interface. The exact value of this

parameter for a particular application is determined by the components in the entire

DRAM system. The DFI specification does not dictate a value but does require that

once this value has been determined, the dfi_rddata_en signal must be asserted based

on this timing parameter.

The t

phy_rdlat

parameter defines the maximum number of cycles allowed from the

assertion of the dfi_rddata_en signal to the assertion of the dfi_rddata_valid signal.

This parameter is specified by the system, but the exact value of this parameter is not

determined by the DFI specification.

These timing parameters (t

rddata_en

and t

phy_rdlat

) must be held constant while

commands are being executed on the DFI bus; however, if necessary, these values may

be changed when the bus is idle. These parameters work together to define a maximum

number of cycles from the assertion of a read command on the DFI control interface to

the assertion of the dfi_rddata_valid signal, indicating the first valid data of the

contiguous read data. Read data may be returned earlier by asserting the

dfi_rddata_valid signal before t

phy_rdlat

cycles have expired. When the signal

dfi_rddata_valid is asserted, the entire DFI read data word must be valid. For the

LPDDR2 DFI, the signal dfi_rddata_dnv must also be sent with the read data signal

dfi_rddata when the dfi_rddata_valid signal is asserted.

For frequency ratio systems, the read data enable signal will be replicated into phase-

specific signals with a suffix of “_pN” that defines the signal value for each phase N of

the DFI PHY clock relative to the DFI clock. The read data, read data valid and read

data not valid signals will be replaced with DFI data word-specific signals with a suffix

of “_wN” with the DFI data word N. For all signal types, the suffix for phase 0/word 0

is optional.

More information on the read data interface is provided in Section 4.4, “Read

Transactions”. The signals and parameters in the read data interface are listed in Table 6

and Table 7.

TABLE 6. Read Data Signals

Signal From Width Default Description

dfi_rddata

or dfi_rddata_wN

PHY DFI Data

Width

Read data bus. Read data is expected to be received at the MC

within t

phy_rdlat

cycles after the dfi_rddata_en signal is asserted.

For frequency ratio systems, the read data bus will be replicated

into DFI data word-specific dfi_rddata_wN buses that define the

read data for each DFI data word. For a 1:2 frequency ratio system,

there are 2 dfi_rddata_wN signals. For a 1:4 frequency ratio

system, there are 4 dfi_rddata_wN signals.

Interface Signal Groups

Denali Software DDR PHY Interface (DFI) Specification, Version 2.1 19 of 100

Denali Software, Inc.

dfi_rddata_en

or dfi_rddata_en_pN

MC DFI Data

Enable

Width

0x0 Read data enable. The dfi_rddata_en signal must be asserted

rddata_en

cycles after the assertion of a read command on the DFI

control interface and remains valid for the duration of contiguous

read data expected on the dfi_rddata bus.

The width of the dfi_rddata_en signal is defined as a DFI term.

Ideally, there will be a single dfi_rddata_en bit for each slice of

memory data. The dfi_rddata_en [0] signal corresponds with the

lowest segment of dfi_rddata signals.

For frequency ratio systems, the read data enable signals will be

replicated into phase-specific dfi_rddata_en_pN signals that

define the read data enable for each phase N of the PHY clock.

dfi_rddata_valid

or dfi_rddata_valid_wN

PHY DFI Read

Data Valid

Width

0x0 Read data valid indicator. The dfi_rddata_valid signal will be

asserted with the read data for the number of cycles that data is

being sent. The timing is the same as for the dfi_rddata bus.

For frequency ratio systems, the read data valid signals will be

replicated into DFI data word-specific dfi_rddata_valid_wN

signals that define the validity of the read data. For a 1:2 frequency

ratio system, there are 2 dfi_rddata_valid_wN signals. For a 1:4

frequency ratio system, there are 4 dfi_rddata_valid_wN signals.

dfi_rddata_dnv

or dfi_rddata_dnv_wN

PHY DFI Data

Width / 8

0x0 DFI data not valid. The timing is the same as for the

dfi_rddata_valid signal.

The dfi_rddata_dnv [0] signal correlates to the dfi_rddata [7:0]

signals, the dfi_rddata_dnv [1] signal correlates to the dfi_rddata

[15:8] signals, etc. If the dfi_rddata bus is not a multiple of 8, then

the uppermost bit of the dfi_rddata_dnv signal corresponds to the

most significant partial byte of data.

For frequency ratio systems, the read data not valid signals will be

replicated into DFI data word-specific dfi_rddata_dnv_wN

signals that define the validity of read data. For a 1:2 frequency

ratio system, there are 2 dfi_rddata_dnv_wN signals. For a 1:4

frequency ratio system, there are 4 dfi_rddata_dnv_wN signals.

This signal is only required for DFI LPDDR2 support.

a. This signal is not meaningful during initialization. Therefore, no default value is required to be maintained for this signal.

b. Since all bits of the dfi_rddata_en signal are identical, the width of the signal on the MC side and the PHY side may be

different; the PHY is not required to use all of the bits.

c. Since all bits of the dfi_rddata_valid signal are identical, the width of the signal on the MC side and the PHY side may be

different; the MC is not required to use all of the bits.

TABLE 6. Read Data Signals

Signal From Width Default Description

Interface Signal Groups

20 of 100 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

3.4 Update Interface

During system operation, the system may require updates to internal settings to

compensate for environmental conditions. To ensure that updates do not interfere with

signals on the DRAM interface, the DFI supports update modes where the DFI read,

write, and control interface are suspended from normal activity. The DFI specification

supports both MC-initiated and PHY-initiated updates. More information on the update

interface is provided in Section 4.5, “PHY Update”.

If a MC initiates an update request by asserting the dfi_ctrlupd_req signal, the request

can be acknowledged or ignored by the PHY. If the request is acknowledged by

asserting the dfi_ctrlupd_ack signal, the protocol described in Section 4.5.1, “MC-

Initiated Update” must be followed. The DFI specification requires the MC to issue

update requests and it specifies a maximum interval (t

ctrlupd_interval

)

at which requests

must be offered. The MC should assert the dfi_ctrlupd_req signal at the end of

memory initialization to signify that the initialization is complete.

If a PHY initiates an update request by asserting the dfi_phyupd_req signal, the request

must be acknowledged by the MC through a dfi_phyupd_ack signal assertion. The DFI

specifies up to 4 different update PHY-initiated request modes. Each mode differs only

in the number of cycles that the DFI interface must be suspended while the update

occurs. During this time, the MC is responsible for placing the system in a state where

the DFI bus is suspended from all activity other than activity specifically related to the

update process being executed. Refer to Section 4.5.2, “PHY-Initiated Update” for more

details on this protocol. The DFI specification does not require the PHY to issue update

requests nor does it specify an interval in which requests must be offered. If the PHY

chooses to offer update requests, it must follow the specified protocol.

TABLE 7. Read Data Timing Parameters

Parameter

Defined

By Min Max Unit Description

phy_rdlat

PHY 0

a. The DFI does not specify a maximum value. The range of values supported is implementation-specific.

DFI PHY

clock

cycles

b. This timing parameter is defined in terms of DFI PHY clock cycles for frequency ratio systems. For matched frequency

systems, a DFI PHY clock is identical to the DFI clock.

Specifies the maximum number of DFI PHY clock cycles allowed

from the assertion of the dfi_rddata_en signal to the assertion of the

dfi_rddata_valid signal.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

rddata_en

System 0

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles from the assertion of

a read command on the DFI to the assertion of the dfi_rddata_en

signal.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

剩余99页未读，继续阅读

succy

粉丝: 2
资源: 7

DDR3 DFI 2.1接口规范详解：信号、时序与功能全面解读

DDR_PHY_Interface_Specification_v5_0.pdf

DFI ddr phy interface 3.1

mipi_CSI-2_specification_v2-1-2018.zip

DDR-PHY-Interface-Specification-v3-1

DDR-PHY-Interface-Specification-v4-0 v5-1

DFI DDR-PHY-Interface-Specification-v5-1 v4-0 v3-1 v3-0

MIPI-D-PHY-specification-v1.1.pdf

phy-interface-pci-express-sata-usb30-architectures-3-1.pdf v5.2

phy-interface-pci-express-sata-usb30-architectures-3-1.pdf

MIPI-D-PHY-Specification-v01-00-00.pdf

最新资源