MAX9288/MAX9290 GMSL Deserializers: 高速多媒体串行链路解串器

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"MAX9288-MAX9290.pdf" MAX9288 和 MAX9290 是由Maxim Integrated推出的高速多媒体串行链路（Gigabit Multimedia Serial Link，GMSL）解串器芯片，主要用于接收GMSL串行器通过50Ω同轴电缆或100Ω屏蔽双绞线（STP）传输的数据，并在输出端将这些数据解串成CSI-2接口的信号。这两款芯片的主要区别在于，MAX9290集成了HDCP（High-bandwidth Digital Content Protection，高带宽数字内容保护）内容保护功能，而MAX9288则不具备此功能。在与GMSL串行器的配合下，这两个解串器可以支持同轴输出，且当配置为STP输入时，它们能够与任何GMSL串行器实现向后兼容，具有良好的灵活性。音频通道方面，它们支持L-PCM I2S立体声，以及TDM模式下的最多8个音频通道，采样率范围从32kHz到192kHz，样本深度可高达32位，满足高质量音频传输的需求。控制通道是MAX9288/MAX9290的一个重要特性，它能在9.6kbps至1Mbps的速率下工作，支持UART-to-UART、UART-to-I2C模式，而在I2C-to-I2C模式下，速率可提升至1Mbps。通过这个控制通道，微控制器（μC）能够在任何时间独立于视频时序编程串行器、解串器以及外围设备的寄存器，同时也方便管理MAX9290的HDCP操作。此外，这两个芯片还包括两个GPIO（General Purpose Input/Output，通用输入/输出）端口，可以用于显示屏的电源控制、背光切换等应用。还有一个持续采样的GPIO输入，能支持触摸屏控制器的中断请求，这对于集成触摸屏功能的显示应用来说非常有用。总体而言，MAX9288和MAX9290是高性能的解串器芯片，适用于高清视频和音频信号的长距离传输，同时提供了丰富的接口选项和强大的控制功能，确保了系统设计的灵活性和可靠性。它们在汽车电子、智能家居、工业自动化等领域的高级多媒体系统中有着广泛的应用潜力。

AVDD18

= V

DVDD18

= V

IOVDD

= 1.8V, V

AVDD3

= 3.3V, T

= +25°C, unless otherwise noted.)

MAX9288/MAX9290 3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

Maxim Integrated

│

www.maximintegrated.com

100

120

140

160

180

200

220

240

260

15 30 45 60 75 90 105

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = OPEN)

toc02

PRBS ON,

COAX MODE,

RGB888,

HDCP ON

2 CHANNELS

EQ OFF

EQ ON

100

120

140

160

180

200

220

240

260

5 20 35 50 65 80

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = HIGH)

toc03

PRBS ON,

COAX MODE,

RGB888,

HDCP ON

2 CHANNELS

EQ OFF

EQ ON

100

120

140

160

180

200

220

240

260

5 15 25 35 45 55 65 75 85 95 105

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = LOW)

toc01

PRBS ON,

COAX MODE,

RGB666,

HDCP ON

2 CHANNELS

EQ OFF

EQ ON

100

120

140

160

180

200

220

240

260

5 15 25 35 45 55 65 75 85 95 105

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = LOW)

toc04

PRBS ON,

COAX MODE,

RGB666,

HDCP ON

4 CHANNELS

EQ OFF

EQ ON

100

120

140

160

180

200

220

240

260

5 20 35 50 65 80

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = HIGH)

toc06

PRBS ON,

COAX MODE,

RGB888,

HDCP ON

4 CHANNELS

EQ OFF

EQ ON

100

120

140

160

180

200

220

240

260

15 30 45 60 75 90 105

SUPPLY CURRENT (mA)

PCLK FREQUENCY (MHz)

SUPPLY CURRENT

vs. PIXEL CLOCK FREQUENCY (BWS = OPEN)

toc05

PRBS ON,

COAX MODE,

RGB888,

HDCP ON

4 CHANNELS

EQ OFF

EQ ON

100

120

0 5 10 15 20 25

PIXEL CLOCK FREQUENCY (MHz)

CABLE LENGTH (m)

MAXIMUM PIXEL CLOCK FREQUENCY

vs. COAX CABLE LENGTH (BER ≤ 10

-10

)

toc07

BER CAN BE AS LOW AS 10

-12

FOR

CABLE LENGTHS LESS THAN 15m

OPTIMUM

PE/EQ

NO PE,

10.7dB EQ

NO PE/EQ

Typical Operating Characteristics

MAX9288/MAX9290 3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated

│

PIN NAME FUNCTION

9 MS

Mode Select with Internal Pulldown to EP. MS sets the control-link mode when CDS = high. Set MS

= low, to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when

CDS = low.

10, 23,

DVDD18

1.8V Digital Power Supply. Bypass DVDD18 to EP with 0.1µF and 0.001µF capacitors as close as

possible to the device with the smaller value capacitor closest to DVDD18.

11 GPIO1 Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD

12 EQS

Equalizer Select Input, with Internal Pulldown to EP. The state of EQS latches upon power-up or

when resuming from power-down mode (PWDN = low). Leave EQS open for 10.7dB equalizer boost

(EQTUNE = 1001). Connect EQS to IOVDD with a 30kΩ resistor for 5.2dB equalizer boost (EQTUNE =

0100).

13 RX/SDA

UART Receive/I

C Serial Data Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is

determined by the state of I2CSEL at power-up. RX/SDA has an open-drain driver and requires a

pullup resistor.

RX: Input of the deserializer’s UART.

SDA: Data input/output of the deserializer’s I

C Master/Slave.

14 TX/SCL

UART Transmit/I

C Serial Clock Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is

determined by the state of I2CSEL at power-up. TX/SCL has an open-drain driver and requires a pullup

resistor.

TX: Output of the deserializer’s UART.

SCL: Clock input/output of the deserializer’s I

C Master/Slave.

15 PWDN

Active-Low, Power-Down Input, with Internal Pulldown to EP. Set PWDN low to enter power-down

mode to reduce power consumption.

16 WS

S/TDM Word-Select Input/Output. Powers up as an I

S output (deserializer provided clock). Set

AUDIOMODE bit = ‘1’ to change WS to an input with internal pulldown to GND and supply WS

externally (system provided clock).

17 SCK

S/TDM Serial-Clock Input/Output. Powers up as an I

S output (deserializer provided clock). Set

AUDIOMODE bit = ‘1’ to change SCK to an input with internal pulldown to GND and supply SCK

externally (system provided clock).

18 SD

S/TDM Serial-Data Output. Disable I

S/TDM encoding to serial data to use SD as an additional

control/data output. Encrypted when HDCP is enabled.

19 ADD2/CNTL2

Address Selection Input/Auxiliary Control Signal Output, with Internal Pulldown to EP. Functions as

ADD2 input at power-up or when resuming from power-down mode (PWDN = low), and switches to

CNTL2 output automatically after power-up.

ADD2: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See

Table 1. Connect ADD2/CNTL2 to IOVDD with a 30kΩ resistor to set high or leave open to set low.

CNTL2: Used only in 32-bit and high-bandwidth mode (BWS = high, open). CNTL2 is mapped from the

GMSL serializer’s CNTL2 or DIN28 input.

Pin Description (continued)

MAX9288/MAX9290 3.12Gbps GMSL Deserializers

for Coax or STP Input and MIPI CSI-2 Output

www.maximintegrated.com

Maxim Integrated

│

PIN NAME FUNCTION

20 HIM/CNTL1

High-Immunity Mode Input/Auxiliary Control Signal Output With Internal Pulldown to EP. Functions

as HIM input at power-up or when resuming from power-down mode (PWDN = low), and switches to

CNTL2 output automatically after power-up.

HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode

(PWDN = low) and is active-high. Connect HIM/CNTL1 to IOVDD with a 30kΩ resistor to set high or

leave open to set low. HIGHIMM can be programmed to a different value after power-up. HIGHIMM in

the serializer must be set to the same value.

CNTL1: Used only in 32-bit and high-bandwidth mode (BWS = high, open). CNTL1 is mapped from the

GMSL serializer’s CNTL1, DIN27, or RES input.

21, 43 IOVDD

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and 0.001µF

capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.

22 CDS

Control Direction Selection Input, with Internal Pulldown to EP. Control link direct selection input

with internal pulldown to EP. Set CDS = low when the control channel master µC is connected at the

serializer. Set CDS = high when the control channel master µC is connected at the deserializer.

24 RES Reserved. Leave unconnected

25, 36 AVDD18

1.8V Analog Power Supply. Bypass AVDD18 to EP with 0.1µF and 0.001µF capacitors as close as

possible to the device with the smaller capacitor closest to AVDD18.

26–29,

32–35

DOUT_+,

DOUT_-

CSI-2 Data Outputs

30, 31 CLK+, CLK- CSI-2 Clock Output

38 ADD1/CNTL3

Auxiliary Control Signal Output/Address Selection Input, with Internal Pulldown to EP. Functions as

ADD1 input at power-up or when resuming from power-down mode (PWDN = low), and switches to

CNTL3 output automatically after power-up.

ADD1: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See

Table 1. Connect ADD1/CNTL3 to IOVDD with a 30kΩ resistor to set high or leave open to set low.

CNTL3: Used only in high-bandwidth mode (BWS = open.

39 ADD0/CNTL0

Auxiliary Control Signal Output/Address Selection Input, with Internal Pulldown to EP. Functions as

ADD0 input at power-up or when resuming from power-down mode (PWDN = low), and switches to

CNTL0 output automatically after power-up.

ADD0: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low).

See Table 1. Connect ADD0/CNTL0 to IOVDD with a 30kΩ resistor to set high or leave open to set low.

CNTL0: Used only in high-bandwidth mode (BWS = open).

40 LOCK

Open-Drain Lock Output, with Internal 60kΩ Pullup to IOVDD. LOCK = high indicates that PLLs are

locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or

an incorrect serial-word-boundary alignment. LOCK is high when PWDN = low.

41 ERR

Error Output. Open-drain data error detection and/or correction indication output with internal 60kΩ

pullup to IOVDD. ERR is high when PWDN is low.

Pin Description (continued)

剩余102页未读，继续阅读

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