i.MX27官方数据手册：低功耗高性能多媒体应用处理器详解

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本文档是Freescale Semiconductor公司关于i.MX27多媒体应用处理器的官方数据手册，发布于2008年1月，处于初步阶段，可能会根据需要进行更改或停止供应。i.MX27是一款低功耗、高性能的应用处理器，适用于各种多媒体应用环境。本手册主要关注该处理器的内部结构、控制器功能以及塑料封装的详细规格。在包装方面，i.MX27采用MAPBGA-404（1816-01）塑料外壳设计，这意味着它具有404个引脚，适用于紧凑型设计。订购信息可在文档第4页的表1中查找，读者应参考该部分获取产品订购的相关细节。 i.MX27与i.MX27L的主要区别在于i.MX27L不具备以下特性：ATA-6硬盘接口、Memory Stick Pro接口、VPU（Video Processing Unit，视频处理单元）、以及MPEG-4/H.263/H.264硬件编码解码器。这意味着i.MX27L可能专为那些对上述特定功能需求不高的应用而设计，但提供了更基础的多媒体处理能力。介绍部分强调了i.MX27/MCIMX27L系列处理器作为产品发展的一部分，旨在提供高效能的同时保持低功耗，这使得它们适合于便携式电子设备、嵌入式系统以及对能源效率有严格要求的场景。手册详细的部分内容将包括处理器架构、CPU核心特性（如ARM Cortex-A8内核、高速缓存和总线接口）、多媒体处理单元（如图像处理器、音频编解码器）、内存管理、I/O接口（如USB、UART、SPI等）、以及电源管理和中断管理等关键组件的详细介绍。此外，还可能涵盖安全特性和外围设备支持，比如GPIO、PWM、以及各种工业标准接口的驱动支持。对于开发者和系统集成者来说，这份数据手册提供了构建基于i.MX27/MCIMX27L平台项目的重要参考资料，确保他们了解如何最有效地利用这些处理器的功能，同时避免由于规格不符导致的问题。i.MX27官方数据手册是一个全面的指南，涵盖了从硬件到软件开发的所有必要信息。

i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

16 Preliminary—Subject to Change Without Notice Freescale Semiconductor

Functional Description and Application Information

— Interpreting buffer descriptors

— Address recognition for receive frames

— Random number generation for transmit collision backoff timer

• The message information block (MIB) in FEC maintains counters for a variety of network events

and statistics. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and

some of the IEEE 802.3 counters.

2.3.14 General Purpose I/O Module (GPIO)

The general-purpose input/output (GPIO) module provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When it is configured as an output, you can write to an internal

of the input by reading the state of an internal register. The GPIO includes all of the general purpose

input/output logic necessary to drive a specific data to the pad and control the direction of the pad using

registers in the GPIO module. The ARM926 is able to sample the status of the corresponding pads by

reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify

interrupt edges as well as generate three active high interrupts.

2.3.15 General Purpose Timer (GPT)

The i.MX27/MX27L processors contains six identical 32-bit general purpose timers (GPT) with

programmable prescalers and compare and capture registers. Each timer’s counter value can be captured

using an external event, and can be configured to trigger a capture event on the rising or/and falling edges

of an input pulse. Each GPT can also generate an event on the TOUT pin, and an interrupt when the timer

reaches a programmed value. Each GPT has an 11-bit prescaler that provides a programmable clock

frequency derived from multiple clock sources, including ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4,

and external clock from the TIN pin. The counter has two operation modes: free-run and restart mode. The

GPT can work in low-power mode.

2.3.16 Inter IC Communication (I

Inter IC communication (I

C) is a two-wire, bidirectional serial bus that provides a simple, efficient

method of data exchange, minimizing the interconnection between devices. This bus is suitable for

applications requiring occasional communications over a short distance between many devices. The

flexible I

C enables additional devices to be connected to the bus for expansion and system development.

The I

C operates up to 400 kbps dependent on pad loading and timing. (For pad requirement details, refer

to Phillips I

C Bus Specification, Version 2.1.) The I

C system is a true multiple-master bus, including

arbitration and collision detection that prevents data corruption if multiple devices attempt to control the

bus simultaneously. This feature supports complex applications with multiprocessor control and can be

used for rapid testing and alignment of end products through external connections to an assembly-line

computer.

Functional Description and Application Information

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor Preliminary—Subject to Change Without Notice 17

2.3.17 IC Identification Module (IIM)

The IC identification module (IIM) provides an interface for reading and in some cases programming

and/or overriding identification and control information stored in on-chip fuse elements. The module

supports laser fuses (L-Fuses) or electrically-programmable poly fuses (e-Fuses) or both.

The IIM also provides a set of volatile software-accessible signals, which can be used for software control

of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism

for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask

revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The

IIM also provides up to 28 volatile control signals and an ability to generate a second 168-bit SCC key.

The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold

the values of signals visible outside the module. Up to eight arrays of fuses (L-Fuses and/or e-Fuses) are

associated with the IIM, but are instantiated outside of it.

The IIM is accessible via an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural

width of the fuse arrays. All registers are 32-bit aligned to enable the module to be instantiated on IP buses

supporting only 32-bit peripherals. A subset of fuses, as well as the software-controlled volatile signals,

are capable of driving top-level nets within the SoC. These signals are hereinafter referred to as

Hardware-Visible Signals, or HW-Visible Signals. These signals are intended for feature enablement and

disablement and similar uses within the device.

Laser fuses can only be blown during chip manufacturing (at the wafer level). The e-Fuses may be blown

under software or JTAG control during the IC final test, in the customer’s factory, or in the field. They

include a mechanism to inhibit further blowing of fuses (write-protect) to support secure computing

environments. The fuse values may also be overridden by software without modifying the fuse element.

Similar to the write-protect functionality, the override functionality can also be permanently disabled. Fuse

banks may also be scan-inhibited on a per-bank basis to prevent reading and programming of fuses through

the JTAG interface.

2.3.18 JTAG Controller (JTAGC)

The JTAG controller (JTAGC) module supports debug access to the ARM926 Platform and tristate enable

of the I/O pads. The overall strategy is to achieve good test and debug features without increasing the pin

count and reducing the complexity of I/O muxing. The JTAG Controller is compatible with IEEE 1149.1

Standard Test Access Port and Boundary Scan Architecture.

2.3.19 Keypad Port (KPP)

The keypad port (KPP) is designed to interface with a keypad matrix with 2-contact or 3-point contact

keys. KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate

software support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed

simultaneously in the keypad. The KPP supports up to 8 × 8 external key pad matrix. Its port pins can be

used as general purpose I/O. Using an open drain design, the KPP includes glitch suppression circuit

design, multiple keys, long key, and standby key detection.

i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

18 Preliminary—Subject to Change Without Notice Freescale Semiconductor

Functional Description and Application Information

2.3.20 Liquid Crystal Display Controller (LCDC)

The liquid crystal display controller (LCDC) provides display data for external gray-scale or color LCD

panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive

color or CSTN), and active-matrix color (active color or TFT) LCD panels.

The LCDC provides the following features:

• Configurable AHB bus width (32-bit/64-bit).

• Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD

panels

• 16 simultaneous gray-scale levels from a palette of 16 for monochrome display

• Support for:

— Maximum resolution of 800 × 600

— Passive color panel:

– 4 (mapped to RGB444) / 8 (mapped to RGB444) / 12 (RGB444) bits per pixel (bpp)

— TFT panel:

– 4 (mapped to RGB666) / 8 (mapped to RGB666) / 12 (RGB444) / 16 (RGB565) / 18

(RGB666) bpp

— 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display,

respectively

— 16 and 256 colors out of a palette of 256 colors for 4 bpp and 8 bpp TFT display, respectively

— True 4096 colors for a 12 bpp display

— True 64K colors for 16 bpp

— True 256K colors for 18 bpp

— 16-bit AUO TFT LCD Panel

— 24-bit AUO TFT LCD Panel

2.3.21 Multi-Master Memory Interface (M3IF)/M3IF-ESDCTL/MDDRC

Interface

The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating

multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the

access to and from the enhanced SDRAM/MDDR memory controller. For the other port interfaces, the

M3IF only arbitrates and forwards the master requests received through the master port gasket (MPG)

interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that

interface with the M3IF include the ARM Platform, FEC, LCDC, H.264, and the USB. The controllers are

the ESDCTL/MDDRC, PCMCIA, NFC, and WEIM.

2.3.22 Multi-Layer AHB Crossbar Switch (MAX)

The ARM926EJ-S processor’s instruction and data buses—and all alternate bus master

interfaces—arbitrate for resources via a 6 × 34 Multi-Layer AHB Crossbar Switch (MAX). There are six

Functional Description and Application Information

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor Preliminary—Subject to Change Without Notice 19

(M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is

uni-directional. All master and slave ports are AHB-Lite compliant.

The design of the crossbar switch enables concurrent transactions to proceed from any master port to any

slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three

independent master requests. If a particular slave port is simultaneously requested by more than one master

port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the

bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration

schemes supported are fixed, programmable fixed, programmable default input port parking, and a round

robin arbitration scheme.

The crossbar switch also monitors the ccm_br input (clock control module bus request), which requests a

bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest

priority. Upon receiving bus grants for all four output ports, the ccm_bg output asserts. At this point, the

clock control and reset module (CRM) can turn off hclk and be assured there are no outstanding AHB

transactions in progress. Once the CRM is granted a port, no other master receives a grant on that port until

the CRM bus request (ccm_br) negates.

2.3.23 Memory Stick Host Controller (MSHC)

The memory stick host controller (MSHC) is located between the AIPI and the Sony Memory Stick and

provides support for data transfers between the i.MX27 processor and the Memory Stick (MS). The MSHC

consists of two sub-modules; the MSHC gasket and the Sony memory stick host controller (SMSC). The

SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick

Ver 1.x and Memory Stick PRO. The gasket connects the AIPI IP bus to the SMSC interface to allow

communication and data transfers via the IP Bus.

NOTE

The i.MX27L does not include the MSHC feature.

The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include

a back-to-back read or write. DMA transfers also take place via the IP Bus interface.

A transfer can be initiated by the DMA or the host (through the AIPI) response to an MSHC DMA request

or interrupt. The SMSC has two DMA address modes—a single address mode and a dual address mode.

The MSHC is set to dual-address mode for transfers with the DMA. In dual-address mode, when the

MSHC requests a transfer with the DMA request (XDRQ), the DMA initiates a transfer to the MSHC.

NOTE

Details regarding the operation of the MSHC module can be found

separately in Memory Stick/Memory Stick PRO Host Controller IP

Specification 1.3.

2.3.24 NAND Flash Controller (NFC)

NAND flash controller (NFC) interfaces standard NAND Flash devices to the i.MX27/MX27L processors

and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bit and

i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

20 Preliminary—Subject to Change Without Notice Freescale Semiconductor

Functional Description and Application Information

16-bit NAND Flash parts with page sizes of 512 Bytes or 2 Kbytes. Its addressing scheme enables it to

access flash devices of almost limitless capacity. The 2-Kbyte RAM buffer of the NAND Flash is used as

the boot RAM during a cold reset (if the i.MX27/MX27L device is configured for a boot to be carried out

from the NAND Flash device). After the boot procedure completes, the RAM is available as buffer RAM.

In addition, the NAND Flash controller provides an X16-bit and X32-bit interface to the AHB bus on the

chip side, and an X8/X16 interface to the NAND Flash device on the external side.

2.3.25 Personal Computer Memory Card International Association

(PCMCIA)

The Personal Computer Memory Card International Association (PCMCIA) provides the PCMCIA 2.1

standard, which defines the usage of memory and I/O devices as insertable and exchangeable peripherals

for personal computers or PDAs. Examples of these types of devices include CompactFlash and WLAN

adapters.

The pcmcia_if host adapter module provides the control logic for PCMCIA socket interfaces, and requires

some additional external analog power switching logic and buffering. The additional external buffers

allow the pcmcia_if host adapter module to support one PCMCIA socket. The pcmcia_if shares its chip

level I/O with the external interface to memory (EIM) pins. Additional logic is required to multiplex the

EIM and the pcmcia_if on the same pins.

2.3.26 Digital Phase Lock Loop (DPLL)

Two on-chip digital phase lock loop (DPLLs) provide clock generation in digital and mixed analog/digital

chips designed for wireless communication and other applications. The DPLLs produce a high-frequency

chip clock signals with a low frequency and phase jitter.

2.3.27 Pulse-Width Modulator (PWM)

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sounds from stored

sample audio images; it can also generate tones. The PWM uses 16-bit resolution and a 4 × 16 data FIFO

to generate sound. The 16-bit up-counter has a source selectable clock with 4 × 16 FIFO to minimize

interrupt overhead. Clock-in frequency is controlled by a 12-bit prescaler for the division of a clock.

Capable of sound and melody generation, the PWM has an active-high or active-low configurable output,

and can be programmed to be active in low-power and debug modes. The PWM can be programmed to

generate interrupts at compare and rollover events.

2.3.28 Real Time Clock (RTC)

The real time clock module (RTC) maintains the system clock, provides stopwatch, alarm, and interrupt

functions, and supports the following features:

• Full clock—days, hours, minutes, seconds

• Minute countdown timer with interrupt

• Programmable daily alarm with interrupt

• Sampling timer with interrupt

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