STM32F7与STM32H7微控制器编程指南

需积分: 50 18 浏览量更新于2024-07-15 收藏 5.13MB PDF 举报

"STM32F7和STM32H7单片机编程手册.pdf" STM32F7和STM32H7系列是基于ARM Cortex-M7处理器的高性能微控制器，由意法半导体（STMicroelectronics）制造。Cortex-M7处理器在Cortex-M家族中处于性能顶端，设计用于满足微控制器市场的各种需求。该处理器的特点包括一个六阶段的超标量流水线，这使得它能够同时处理多个指令，从而提高了执行效率。处理器的系统和内存接口非常灵活，包括高级扩展接口（AXI）、先进高速总线（AHB）以及缓存和紧耦合存储器（TCM）。这些特性使得STM32F7和STM32H7在处理整数运算、浮点运算和数字信号处理（DSP）任务时表现出卓越的性能。此外，Cortex-M7支持对多个内存接口的加载/加载和加载/存储指令对的双问题，这意味着它可以并行处理数据读取和写入操作，进一步提升了处理速度。 STM32F7和STM32H7系列微控制器继承了Cortex-M系列处理器的易用性，采用C语言友好的程序员模型，确保了与现有Cortex-M处理器的二进制兼容性。这意味着开发者可以轻松地将原有的Cortex-M代码迁移到新的平台，而无需进行大量的代码修改。编程手册详细介绍了STM32F7和STM32H7系列处理器的编程模型、指令集以及核心外围设备。对于应用级和系统级软件开发者来说，这份手册是一个宝贵的资源，它提供了全面的开发指南，帮助开发者充分利用这些微控制器的潜能。手册涵盖的内容可能包括但不限于：中断系统、异常处理、存储器管理、外设接口配置、电源管理和调试工具的使用等。通过深入学习这份编程手册，开发者不仅可以了解如何有效地编写和优化代码，还能掌握如何针对特定应用优化微控制器的性能，例如在实时操作系统（RTOS）环境下工作，或者实现高效的嵌入式算法。STM32F7和STM32H7系列微控制器结合了高性能、低功耗和丰富的外设集，是物联网、工业自动化、医疗设备、消费电子等多种领域应用的理想选择。

About this document PM0253

16/252 DocID028474 Rev 4

density and reduced program memory requirements. The Cortex

-M7 instruction set

provides the exceptional performance expected of a modern 32-bit architecture, with the

high code density of 8-bit and 16-bit microcontrollers.

The Cortex

-M7 processor closely integrates a configurable NVIC, to deliver industry-

leading interrupt performance. The NVIC includes a Non Maskable Interrupt (NMI), and

provides up to 256 interrupt priority levels. The tight integration of the processor core and

NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the

interrupt latency. This is achieved through the hardware stacking of registers, and the ability

to suspend load-multiple and store-multiple operations. Interrupt handlers do not require

wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain

optimization also significantly reduces the overhead when switching from one ISR to

another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to be rapidly powered down while still

retaining program state.

The reliability is increased with automatic fault detection and handling built-in. The

Cortex

-M7 processor uses ECC and SECDED on accesses to memory and has Memory

Build-in Self Test (MBIST) capability. The Cortex

-M7 processor is dual-redundant, which

means it can operate in lock-step. The MCU vendor determines the reliability features

configuration and therefore this can differ across different devices and families.

To increase instruction throughput, the Cortex

-M7 processor can execute certain pairs of

instructions simultaneously. This is called dual issue.

1.3.1 System level interface

The Cortex

-M7 processor provides multiple interfaces using AMBA

technology to provide

high speed, low latency memory accesses. It supports unaligned data accesses.

The Cortex

-M7 processor has an MPU that provides fine grain memory control, enabling

applications to utilize multiple privilege levels, separating and protecting code, data and

stack on a task-by-task basis. Such requirements are becoming critical in many embedded

applications such as automotive.

1.3.2 Integrated configurable debug

The Cortex

-M7 processor implements a complete hardware debug solution. This provides

high system visibility of the processor and memory through either a traditional JTAG port or

a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small

package devices. The MCU vendor determines the debug feature configuration and

therefore this can differ across different devices and families.

For system trace the processor integrates an Instrumentation Trace Macrocell (ITM)

together with data watchpoints and a profiling unit. To enable simple and cost-effective

profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a

stream of software-generated messages, data trace, and profiling information through a

single pin.

The optional CoreSight technology components, Embedded Trace Macrocell

™

(ETM),

delivers unrivalled instruction trace and data trace capture in an area far smaller than

traditional trace units, enabling many low cost MCUs to implement full instruction trace for

the first time.

DocID028474 Rev 4 17/252

PM0253 About this document

The Breakpoint Unit provides up to eight hardware breakpoint comparators that debuggers

can use.

1.3.3 Cortex

-M7 processor features and benefits summary

• Tight integration of system peripherals reduces area and development costs.

• Thumb instruction set combines high code density with 32-bit performance.

• IEEE754-compliant single-precision and double-precision Floating-Point Unit (FPU).

• Power control optimization of system components.

• Integrated sleep modes for low-power consumption.

• Fast code execution permits slower processor clock or increases sleep mode time.

• Hardware division and fast digital-signal-processing orientated multiply accumulate.

• Saturating arithmetic for signal processing.

• Deterministic, high-performance interrupt handling for time-critical applications.

• MPU for safety-critical applications.

• Arm Cortex

-M7 with instruction cache and data cache

• Memory system features such as caches, Tightly-Coupled Memory (TCM) with DMA

port, and a high performance AXI external memory interface.

• Dedicated AHB slave (AHBS) interface for system access to TCMs

• Extensive debug and trace capabilities:

– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for

debugging, tracing, and code profiling.

1.3.4 Cortex

-M7 processor core peripherals

The Cortex

-M7 processor core peripherals are:

Nested Vectored Interrupt Controller

The NVIC is an embedded interrupt controller that supports low latency interrupt

processing.

System Control Block

The System Control Block (SCB) is the programmers model interface to the

processor. It provides system implementation information and system control,

including configuration, control, and reporting of system exceptions.

Integrated instruction and data caches

The instruction and data caches provide fast access to frequently accessed data

and instructions, providing support for increased average performance when using

system based memory.

System timer

The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time

Operating System (RTOS) tick timer or as a simple counter.

Memory Protection Unit

The Memory Protection Unit (MPU) improves system reliability by defining the

memory attributes for different memory regions. It provides up to 8 different

regions, and an optional predefined background region.

DocID028474 Rev 4 19/252

PM0253 The Cortex-M7 processor

2 The Cortex-M7 processor

2.1 Programmers model

This section describes the Cortex

-M7 programmers model. In addition to the individual

core register descriptions, it contains information about the processor modes and privilege

levels for software execution and stacks.

2.1.1 Processor mode and privilege levels for software execution

The processor modes are:

The privilege levels for software execution are:

In Thread mode, the CONTROL register controls whether software execution is privileged or

unprivileged, see

CONTROL register on page 27. In Handler mode, software execution is

always privileged.

Only privileged software can write to the CONTROL register to change the privilege level for

software execution in Thread mode. Unprivileged software can use the

SVC instruction to

make a supervisor call to transfer control to privileged software.

2.1.2 Stacks

The processor uses a full descending stack. This means the stack pointer holds the address

of the last stacked item in memory. When the processor pushes a new item onto the stack, it

decrements the stack pointer and then writes the item to the new memory location. The

processor implements two stacks, the main stack and the process stack, with a pointer for

each held in independent registers, see

Stack pointer on page 21.

In Thread mode, the CONTROL register controls whether the processor uses the main

stack or the process stack, see

CONTROL register on page 27. In Handler mode, the

processor always uses the main stack. The options for processor operations are:

Thread mode Executes application software. The processor enters Thread mode

when it comes out of reset.

Handler mode Handles exceptions. The processor returns to Thread mode when it has

finished all exception processing.

Unprivileged The software:

• Has limited access to system registers using the

MSR

and

MRS

instructions, and cannot use the

CPS

instruction to mask interrupts.

• Cannot access the system timer, NVIC, or system control block.

• Might have restricted access to memory or peripherals.

Unprivileged software executes at the unprivileged level.

Privileged The software can use all the instructions and has access to all

resources.

Privileged software executes at the privileged level.

剩余251页未读，继续阅读

weixin_47201184

粉丝: 0
资源: 4

STM32F7与STM32H7微控制器编程指南

STM32F7编程手册.zip

STM32H7开发指南-寄存器版本_V1.0.pdf

stm32F7数据手册

STM32选型手册.pdf.pdf.pdf

电子-STM32F7xx.pdf

STM32F7全系列STM32单片机F7系列原理图封装库AD库集成库 ALTIUM库(73个器件).zip

STM32 32位ARM单片机选型手册.zip

LAN8720网口驱动STM32F7系列单片机驱动程序.zip

STM32F767驱动TFT LCD电容触摸屏（4.3寸，800X480分辨率）【支持STM32F7系列单片机】.zip

电子-STM32F302xx和STM32F303xx数据手册.pdf

最新资源