DW1000 UWB定位技术用户指南：配置与编程详解

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本资源是DW1000用户手册，由Decawave有限公司发布于2017年，版本号为2.15。这是一份详尽的指南，旨在帮助用户了解并操作DW1000超宽带（UWB）无线传输器。手册主要涵盖了DW1000设备的各个方面，包括其介绍、接口配置、工作状态、消息传输与接收、媒体访问控制（MAC）硬件功能等。 1. 关于DW1000 这部分首先概述了DW1000的基本特性，它是一款高效、低功耗的UWB解决方案，适用于需要高精度定位、短距离通信的场景，如物联网(IoT)设备、可穿戴设备等。DW1000以其高速数据传输、低功耗和抗干扰能力著称。 2. 使用与配置指南手册详细介绍了如何正确使用和配置DW1000。用户需要了解设备的启动过程，包括电源-on-reset (POR)以及默认配置。此外，还讨论了如何设置基本的通信参数，如数据帧结构、延迟传输和高速传输模式。 3. 消息传输这部分详细解释了不同类型的传输，如基础传输、带有时间戳的传输、延迟传输以及支持更长数据包的传输。此外，还有针对高速数据传输的最佳实践和注意事项，确保数据在复杂环境中能准确无误地发送。 4. 消息接收接收部分同样重要，介绍了基础接收机制、延迟接收处理、双缓冲机制以及低功耗监听模式。低功率嗅探模式则允许设备在节能状态下进行数据捕获，而在诊断模式下，可以评估接收到的数据质量和RX时间戳的准确性。 5. MAC硬件特性这部分深入探讨了DW1000的MAC硬件功能，包括循环冗余检查(CRC)以确保数据的完整性和帧过滤功能，这些对于确保数据传输的可靠性和网络效率至关重要。此外，自动功能的介绍有助于用户更好地利用DW1000的高级特性。这份DW1000用户手册提供了一个全面的操作指南，无论是初次接触DW1000的用户还是经验丰富的开发人员，都能从中获取所需的技术细节和最佳实践，以便优化设备性能和通信质量。通过阅读和遵循这份手册，用户能够充分利用DW1000 UWB技术的优势，提升系统的稳定性和效能。

DW1000 User Manual

Version 2.15

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2.3.2 Overview of main operational states

Table 1: Main DW1000 operational states / modes

State Name

State Description

OFF

In the OFF state the DW1000 is completely powered off, with no voltages applied to

any of its input pins. Power consumption = 0 µA. No I/O pins should be driven or

power will leak through the I/O cells.

WAKEUP

During the WAKEUP state the crystal oscillator and the band-gap are enabled. After

approximately 4 ms the digital LDO will be enabled and the RSTn (output) will de-

assert allowing the DW1000 to enter the INIT state.

INIT

In the INIT state the main crystal oscillator is running. The raw 38.4 MHz XTAL

oscillator frequency is divided by 2 to give a 19.2 MHz internal clock called XTI. In the

INIT state digital circuitry of the DW1000 is fed from this 19.2 MHz XTI clock.

If the DW1000 has entered INIT state from a SLEEP or DEEPSLEEP state, (or as a result

of a reset), then the register configurations can be automatically restored from the

AON memory array.

Then the DW1000 turns on the CLKPLL and after 5 µs the CLKPLL will be locked and

the DW1000 will automatically transition into the IDLE state.

SPI accesses from an external microcontroller are possible in the INIT state, but these

are limited to a SPICLK input frequency of no greater than 3 MHz. Care should be

taken not to have an active SPI access in progress at the CLKPLL lock time (i.e. at t =

5 µs) when the automatic switch from the INIT state to the IDLE state is occurring,

because the switch-over of clock source can cause bit errors in the SPI transactions.

It is possible to return to the INIT state from the IDLE state under register control by

selecting the XTAL as the clock source and by disabling what is known as sequencing

so the device does not automatically transfer into the IDLE state.

IDLE

In the IDLE state the DW1000 internal clock generator CLKPLL is locked running and

ready for use but is gated off to most circuitry to minimize power consumption. In the

IDLE state SPI communications can operate at up to 20 MHz, the maximum SPICLK

frequency. In the IDLE state the analog receive and transmit circuits are powered

down. The external host can control the DW1000 to initiate a transmission or

reception and thus cause the DW1000 to progress into TX state or RX state

respectively. If a delayed TX or RX operation is initiated (see section 3.3 – Delayed

Transmission and 4.2 – Delayed Receive) then the DW1000 will stay in the IDLE state

until the delayed time has elapsed, after which it will enter the TX state or RX state.

DW1000 User Manual

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State Name

State Description

SLEEP

In the SLEEP state the IC consumes < 1 µA from the external power supply inputs. All

internal LDOs are turned off. In the SLEEP state the DW1000 internal low powered

ring oscillator is running and is used to clock the sleep counter whose expiry is

programmed to “wake up” the DW1000 and progress into the WAKEUP state. While in

SLEEP power should not be applied to GPIO, SPICLK or SPIMISO pins as this will cause

an increase in leakage current.

DEEPSLEEP

With the exception of the OFF state, the DEEPSLEEP state is the lowest power state of

the device.

In DEEPSLEEP all internal circuitry is powered down with the exception of the always-

on memory which can be used to hold the device configuration for restoration on

wakeup

Once in DEEPSLEEP the DW1000 remains there until the occurrence of a wakeup

event. This can be either:

1. the SPICSn line pulled low or

2. the WAKEUP line driven high

for the duration quoted in the DW1000 data sheet (nominally 500 μs).

It is also recommended to use the SLP2INIT or CPLOCK event status bits (in Register

file: 0x0F – System Event Status Register) to drive the IRQ interrupt output line high to

confirm the wake-up.

Once the DW1000 has detected a wakeup event it progresses into the WAKEUP state.

While in DEEPSLEEP power should not be applied to GPIO, SPICLK or SPIMISO pins as

this will cause an increase in leakage current.

TX state

In the TX state the DW1000 actively transmits a frame containing the contents of the

transmit buffer on the configured RF channel with the configured transmit parameters

(PRF, data rate, preamble code etc.)

Once the frame transmission is complete the DW1000 may enter one of three modes

depending on the programmed configuration.

After the frame transmission is complete the DW1000 will return to the IDLE state

unless the ATXSLP bit is set (in Sub-Register 0x36:04 – PMSC_CTRL1) in which case the

DW1000 will enter the SLEEP or DEEPSLEEP state automatically, (as long as no host

interrupts are pending).

Note that it is not possible to be in the TX and RX states simultaneously – the DW1000

is a half-duplex transceiver device.

DW1000 User Manual

Version 2.15

Page 17 of 244

State Name

State Description

RX state

In the RX state, the DW1000 receiver is active, either hunting for preamble or (once it

has detected preamble) actively receiving preamble searching for SFD, and

subsequently receiving the PHR, decoding it and receiving the data part of the frame.

In the RX state, the RF synthesiser and all RX blocks are active. After an event that ends

the reception, (either a good frame RX, or some error or timeout event that aborts

reception) the DW1000 will return to the IDLE state unless the ARXSLP bit is set (in Sub-

DEEPSLEEP state automatically (as long as no host interrupts are pending).

Note that it is not possible to be in the RX and TX states simultaneously – the DW1000

is a half-duplex transceiver device.

SNOOZE

The SNOOZE state is similar to the INIT state except that a counter is running to cause

the DW1000 to automatically go to the RX state (via INIT and IDLE) when the counter

expires. The snooze count times are in units of the raw 19.2 MHz XTI clock rate, (since

the 125 MHz digital PLL clock is not running).

2.4 Power On Reset (POR)

When the external power source is applied to the DW1000 for the first time, the internal Power On Reset

(POR) circuit compares the externally applied supply voltage to an internal power-on threshold

(approximately 1.5 V), and once this threshold is passed the crystal oscillator is enabled and the external

device enable pin EXTON is asserted. An internal counter running off the low power oscillator is used to hold

the DW1000 in reset to ensure that the crystal oscillator is stable before it gets used. Once the digital reset is

de-asserted the digital core wakes up and enters the WAKEUP state. From this state it will automatically turn

on the CLKPLL and wait for it to lock before entering the IDLE state.

IDLE

INIT

OFF

WAKEUP

CLKPLL locked

Crystal stable,

RSTn=1

POWERON

VDDBATT

EXTON

XTAL

VDDDIG

RSTn

por

SPI comms

up to 3MHz

SPI comms up

to max SPI frequency

Battery Inserted

VDDBATT switched on

300µs

4ms

5µs

7µs

CLKPLL

Lock

CLKPLL

enabled

SPI comms not advised

as PLL locks

DW1000 User Manual

Version 2.15

Page 18 of 244

Figure 9: Timing diagram and power profile for cold start POR

2.4.1 SLEEP and DEEPSLEEP

In the DW1000 very low power DEEPSLEEP state, the IC is almost completely powered down except for a

small amount of memory necessary to maintain IC configurations. This is the lowest power mode of the IC

where the power drain is < 100 nA. To wake the IC from DEEPSLEEP requires an external agent to assert the

WAKEUP input line or the external host microprocessor to initiate an SPI transaction to assert the SPICSn

input.

The DW1000 also includes a low power SLEEP state where the IC can wake itself from sleeping as a result of

the elapsing of a sleep timer that is running from a low-powered ring oscillator internal to the DW1000 IC.

In this SLEEP state the power drain is < 1 µA. The DW1000 may wake from SLEEP state when the sleep timer

elapses. The WAKEUP or SPICSn inputs may also be used to wake the device.

The frequency of the low power oscillator is dependent on process variations within the IC, but is generally

somewhere in between 7,000 and 13,000 Hz. There are facilities within the IC to measure the length of an

LP oscillator cycle, in counts of the IC crystal oscillator divided by two, (i.e. this is 38.4 MHz ÷ 2, or 19.2 MHz).

2.4.1.1 Waking from sleep

The return from SLEEP and DEEPSLEEP modes, is via

 Driving the WAKEUP pin high for approximately 500 μs, (assuming the WAKE_PIN configuration bit is

set in Sub-Register 0x2C:06 – AON_CFG0).

 Driving the SPICSn pin low for approximately 500 μs, (assuming the WAKE_SPI configuration bit is set

in Sub-Register 0x2C:06 – AON_CFG0). This can be achieved by doing a dummy SPI read of sufficient

length.

NOTE: When using the SPICSn pin to wake up the device it is important that the SPIMOSI line is

held low for the duration of the SPICSn to ensure that a spurious write operation does not occur.

In addition return from SLEEP also occurs when

 The internal sleep timer counter expires, (assuming the WAKE_CNT configuration is bit is set in Sub-

In all of three wakeup cases the device is returned to the IDLE state by default but additional state

transitions can be automatically enacted thereafter depending on configurations.

2.4.1.2 Configuration register preservation

Prior to entering the SLEEP and DEEPSLEEP states and prior to exiting the WAKEUP state, the main DW1000

configurations are copied to and from an Always-On memory (AON). Power is maintained to AON memory

at all times, even in SLEEP and DEEPSLEEP states. The copying of configuration data (saving or restoring)

takes about 7 µs to complete. The detail of which configurations are saved and restored is given in Table

DW1000 User Manual

Version 2.15

Page 19 of 244

46: Configurations maintained in the AON. Restoration of configurations during the WAKEUP state is only

done if the ONW_LDC configuration bit is set in 7.2.45.1 – Sub-Register 0x2C:00 – AON_WCFG.

Note: The host system should avoid SPI access to general system registers or OTP Memory during the

copying period to prevent any conflicts occurring. Access to the TX (or RX) buffer is not restricted during this

period.

2.4.1.3 Automatically loading LDO calibration data from the OTP

When waking from SLEEP or DEEPSLEEP it is necessary to load the LDOTUNE_CAL value from the OTP if it has

been programmed during IC production test calibration. To confirm if the LDOTUNE_CAL has been

programmed first read the OTP address 0x4. If this reads back as non-zero (only the first byte needs to be

checked) then the device has been calibrated and the ONW_LLDO bit in Sub-Register 0x2C:00 – AON_WCF

must be set. This will allow the OTP parameter LDOTUNE_CAL to be automatically copied over to the

required register (Sub-Register 0x28:30 – LDOTUNE) each time the DW1000 wakes up. If the OTP address

0x4 reads back as zero, then the ONW_LLDO bit must not be set.

2.4.2 Specific state sequences supported by the DW1000

The DW1000 supports a number of state sequences intended to minimize power consumption in certain

applications. These are: -

Mode Name

Mode Description

SNIFF MODE

In SNIFF mode the DW1000 alternates between the RX (on) and the IDLE (off) states.

Further details on this mode are given in section 4.5.1 – SNIFF.

LOW DUTY

CYCLE SNIFF

MODE

In Low duty-cycle SNIFF mode, where the off time is larger, the DW1000 can be

configured to spend this off time in the INIT state which is lower power than the IDLE

state (used for the off period of a SNIFF). Further details of this mode are given in

section 4.5.2 – Low duty-cycle SNIFF.

LOW POWER

LISTENING

Low-Power Listening mode is a special mode where the receiver spends most its time

in a low power (SLEEP or DEEPSLEEP) state only waking up occasionally to sample the

air for a message. This feature is described in detail in section 4.4 – Low-Power

Listening

2.5 Default Configuration on Power Up

DW1000 is a highly configurable transceiver with many features. The register reset values have been

selected with the intention of minimising user configuration required. The default configuration may be

summarised as being channel 5, preamble code 4 and mode 2. Channel numbers and preamble codes are as

specified in the standard, IEEE 802.15.4-2011 [1] and mode 2 is as specified in the DW1000 data sheet

modes and comprises the following configurations:

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