Atheros AR9280 芯片详细规格与开发指南

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"A9280产品规格详细介绍了这款芯片的特性，包括其在无线局域网络（WLAN）中的应用，特别是在2.4GHz和5GHz频段的802.11n标准下的高性能2x2多输入多输出（MIMO）配置。该芯片由Atheros Communications, Inc.设计，集成了多种协议的媒体访问控制器（MAC）、基带处理器和模数转换器等关键组件，旨在提供可靠的连接质量和最大化的传输速率与覆盖范围。" 在Atheros AR9280芯片中，其主要特点和功能包括： 1. **单芯片解决方案**：AR9280是一款高度集成的芯片，将MAC、基带处理器和射频（RF）部分集成在一个单一的硅片上，降低了硬件成本，提高了系统的可靠性和效率。 2. **2x2 MIMO技术**：支持802.11n标准的2x2 MIMO配置，通过使用两个独立的数据流在空间中同时传输和接收数据，显著提升了无线网络的吞吐量和范围。 3. **多协议支持**：内置的MAC能够处理多种无线协议，不仅限于802.11n，可能还包括802.11a/b/g等，确保了对不同标准的兼容性。 4. **高性能基带处理器**：处理复杂的无线信号处理任务，包括纠错编码、调制解调以及物理层的各种算法，以实现高速无线连接。 5. **模拟到数字转换**：芯片内部的模数转换器负责将接收到的模拟无线信号转化为数字信号，以便进一步处理和解码，确保数据准确无误地传输。 6. **PCI Express接口**：AR9280通过PCI Express接口与主机系统通信，提供了高速的数据传输通道，减少了延迟，提高了整体系统性能。 7. **频段支持**：同时支持2.4GHz和5GHz频段，提供了更广泛的无线覆盖和避免2.4GHz频段拥挤的可能性。 8. **专有技术**：Atheros的专利技术如Signal-Sustain Technology (SST)和Super AG可能被整合在AR9280中，以提升无线连接的稳定性、信号强度和整体用户体验。 9. **商标信息**：提到了Atheros公司的多个注册商标，表明了公司在无线通信领域的创新和技术领先地位。 A9280芯片是为高性能、高稳定性的无线网络应用而设计的，适用于需要强大链接质量和最大传输距离的无线设备，如路由器、网卡或移动设备。其综合特性使得它在当时的市场上具有竞争力，并且对于开发驱动程序的工程师来说，详细了解其寄存器描述是至关重要的。

16 • AR9280 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

16 • October 2009 COMPANY CONFIDENTIAL

3.3 Descriptor Format

The transmit (Tx) descriptor format contains

24 32-bit words and the receive (Rx) descriptor

13 32-bit words (see Table 3-1).

The first two words of the descriptor point to

the next descriptor in the linked list and to the

data buffer associated with the descriptor.

Other words carry additional control

information that affects how the MAC

processes the frame and its data.

A descriptor is required to be aligned on a

32-bit boundary in host memory, although best

performance is achieved if the descriptor is

aligned on a cache-line boundary. The MAC

uses the final two words to report status

information back to the host. See:

Table Description

Table 3-1 DMA descriptor format

Table 3-2 Tx control descriptor format

(words 2–13)

Table 3-3 Tx status descriptors

(words 14–23)

Table 3-4 Rx control descriptor

(words 2–3)

Table 3-5 Rx status descriptor

(words 4–12)

Table 3-1. DMA Descriptor Format

Word Bits Field Name Description

0 31:0 link_ptr Link pointer. Contains the address of the next descriptor to be used; must

be 32-bit aligned (bits [1:0] must be 0)

1 31:0 buf_ptr Data buffer pointer. Contains the starting address of the data buffer

associated with this descriptor. A Tx data buffer can begin at any byte

address. A Rx data buffer must be aligned on a 32-bit boundary in host

memory, although best performance is achieved if the Rx data buffer is

cache-line aligned.

(Cache-line size varies from system to system.)

2–13 (Tx)

2–3 (Rx)

31:0 Host-to-

DMA engine

control

information

Additional control information is passed from host to DMA engine. The

format of these words varies depending on whether the descriptor is being

used to Tx a frame from host to PCU, or Rx a frame from PCU to host.

(See Table 3-2 on page 17, and Table 3-4 on page 26 for details.)

14–23 (Tx)

4–12 (Rx)

31:0 DMA

completion

status

information

Status information reported by the DMA engine when it has finished

processing a descriptor. As with the control information, the format of the

status information differs between Tx and Rx descriptors.

(See Table 3-3 on page 23, and Table 3-5 on page 26 for details.)

Atheros Communications, Inc. AR9280 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 17

COMPANY CONFIDENTIAL October 2009 • 17

The Tx descriptor format for words 2 through

13 is described in Table 3-2.

Table 3-2. Tx Control Descriptor Format (Words 2–13)

Word Bits Field Name Description

2 11:0 frame_length Frame length

Specifies the length, in bytes, of the entire MAC frame, including the frame

check sequence (FCS), initialization vector (IV), and integrity check value

(ICV) fields.

12 vmf Virtual more fragment

If this bit is set, bursting is enabled for this frame. If no burst is in progress, it

initiates a CTS-protected burst if cts_enable is set. If a previous burst is in

progress, it ignores the cts_enable bit and assumes the burst is protected.

13 RES Reserved

14 low_rx_chain When set to 1, indicates that the Rx chain mask switches to low power mode

after transmitting this frame.

15 clear_retry Setting this bit disables the retry bit from being set in the Tx header on a

frame retry (applies to both aggregate and non-aggregate frames).

21:16 tpc_0 Tx power control for series 0

These bits pass unchanged to the baseband, where they are used to control

the transmit power for the frame.

22 rts_enable Request to send (RTS) enable. At most, one of the “rts_enable” and

“cts_enable” bits may be set; it is illegal to set both.

set PCU transmits the frame using the RTS/CTS protocol

clear PCU transmits the frame using the contention/backoff protocol

23 veol Virtual end-of-list flag

When set, indicates that the QCU should act as though the descriptor had a

NULL LinkPtr, even if the LinkPtr is not NULL. Must be valid in the final

descriptor of a frame and must be clear for all other descriptors of the frame.

24 clear_dest_mask Clear destination mask bit flag

If set, instructs the PCU and DCU to clear the destination mask bit at the

index specified by the DestIdx field.

28:25 RES Reserved

29 int_req Interrupt request flag

Set to one by the driver to request that the DMA engine generate an interrupt

upon completion of the frame to which this descriptor belongs.

Note that this field must be valid and identical for all descriptors of the

frame; that is, all descriptors for the frame must have this flag set, or all

descriptors for the frame must have this flag clear.

30 dest_index_valid Destination index valid flag

Specifies whether the contents of the DestIdx field are valid.

31 cts_enable Proceed frame with CTS flag

If set, the PCU first sends a CTS before sending the frame described by the

descriptor. Used for 802.11g and Atheros XR frames to quiet legacy stations

before sending a frame the legacy stations cannot interpret (even at the PHY

level). At most, one of the “rts_enable” and “cts_enable” bits may be set; it is

illegal to set both bits.

20 • AR9280 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

20 • October 2009 COMPANY CONFIDENTIAL

5 7:0 tx_rate0 Tx rate for transmission series 0.

15:8 tx_rate1 Tx rate for transmission series 1. See the rate table in “tx_rate0”.

23:16 tx_rate2 Tx rate for transmission series 2. See the rate table in “tx_rate0”.

31:24 tx_rate3 Tx rate for transmission series 3. See the rate table in “tx_rate0”.

6 14:0 packet_duration0 Packet duration 0 (in μs)

Duration of the actual Tx frame associated with TXRate0. This time does not

include RTS, CTS, ACK, or any associated SIFS.

15 rts_cts_qual0 Qualifies “rts_enable” or “cts_enable” in the Tx descriptor for Tx series 0.

1 Default behavior with respect to “rts_enable” and “cts_enable”

30:16 packet_duration1 Packet duration 1 (in μs)

Duration of the actual Tx frame associated with TXRate1. This time does not

include RTS, CTS, ACK, or any associated SIFS.

31 rts_cts_qual1 Qualifies “rts_enable” or “cts_enable” in the Tx descriptor for Tx series 1.

1 Default behavior with respect to “rts_enable” and “cts_enable”

Table 3-2. Tx Control Descriptor Format (Words 2–13) (continued)

Word Bits Field Name Description

Value Desc Value Desc

0x1–0x7 RES 0x18 CCK_11Mb_L

0x8 OFDM_48Mb 0x19 CCK_5_5Mb_L

0x9 OFDM_24Mb 0x1A CCK_2Mb_L

0xA OFDM_12Mb 0x1B CCK_1Mb_L

0xB OFDM_6Mb 0x1C CCK_11Mb_S

0xC OFDM_54Mb 0x1D CCK_5_5Mb_S

0xD OFDM_36Mb 0x1E CCK_2Mb_S

0xE OFDM_18Mb

0xF OFDM_9Mb

Value

[1]

[1]All values that are not listed here are reserved. Note that for the short guard

interval (GI = 1), HT20 mode is not allowed.

Desc Stream

HT20 GI = 0

(Mbps)

HT40 GI = 0

(Mbps)

HT40 GI = 1

(Mbps)

0x80 MCS 0 1 6.5 13.5 15

0x81 MCS 1 1 13 27 30

0x82 MCS 2 1 19.5 40.5 45

0x83 MCS 3 1 36 54 60

0x84 MCS 4 1 39 81 90

0x85 MCS 5 1 52 108 120

0x86 MCS 6 1 58.5 121.5 135

0x87 MCS 7 1 65 135 150

0x88 MCS 8 2 13 27 30

0x89 MCS 9 2 26 54 60

0x8A MCS 10 2 39 81 90

0x8B MCS 11 2 52 108 120

0x8C MCS 12 2 78 162 180

0x8D MCS 13 2 104 216 240

0x8E MCS 14 2 117 243 270

0x8F MCS 15 2 130 270 300

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