PCI Express 2.0 规范详解

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"PCI Express Base Specification Revision 2.0 是一份英文版的技术规范，详细介绍了PCI Express 2.0版本的标准，适用于需要理解该技术的人群。文档包含了自2002年以来的修订历史，旨在提供5.0 GT/s的数据速率，并整合了批准的错误修正和工程变更通知（Errata and ECNs）。 PCI Express（PCIe）是一种高速接口标准，用于连接计算机系统中的外部设备，如显卡、网卡和硬盘等。它是由PCI特殊兴趣小组（PCI-SIG）制定和维护的。PCIe 2.0是该标准的一个重要里程碑，相比于之前的1.1版本，其数据传输速率翻倍，达到5.0 GT/s（吉比特每秒），这显著提高了设备间的通信速度和系统的整体性能。该规范的修订历史显示，PCIe 2.0是在2006年12月20日发布的，之前经历了1.0和1.1的迭代，不断修正错误并改进设计。值得注意的是，PCI-SIG明确声明不对其文档的使用、其中包含的信息，或可能出现的错误承担任何责任，也不承诺更新此文档中的信息。如果需要获取最新修订版的规范或有关PCI Express Base Specification的问题，可以联系PCI-SIG的会员服务部门或技术支持团队。 PCIe 2.0规范的关键特性包括： 1. 更高的数据传输速率：与PCIe 1.x的2.5 GT/s相比，PCIe 2.0提供了双倍的数据传输速率，达到5.0 GT/s，每个通道可实现1GB/s的双向传输。 2. 位宽不变：尽管速率提升，PCIe 2.0保持了与1.x版本相同的x1、x2、x4、x8、x16和x32通道宽度，确保了向后兼容性。 3. 改进的信号完整性：为了在更高的数据速率下保持信号质量，PCIe 2.0引入了增强的信号处理技术和物理层（PHY）优化。 4. 功耗管理：支持低功耗状态，以适应移动设备和能源效率的需求。 5. 错误处理和恢复机制：包括错误检测和报告，以及错误恢复策略，以提高系统的可靠性和稳定性。 PCIe 2.0规范的实施对硬件开发者、系统架构师以及数据中心管理者至关重要，因为它定义了接口的电气、机械和协议规格，确保不同厂商的PCIe设备能够无缝协作。这份文档是理解和开发PCI Express 2.0设备的基础，对于深入学习PCI Express技术的人来说是宝贵的参考资料。"

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FIGURE 1-1: PCI EXPRESS

LINK.................................................................................................... 33

FIGURE 1-2: EXAMPLE

TOPOLOGY................................................................................................ 35

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A

SWITCH ................................................................. 39

FIGURE 1-4: HIGH-LEVEL LAYERING

DIAGRAM ........................................................................... 41

FIGURE 1-5: PACKET FLOW THROUGH THE

LAYERS ..................................................................... 42

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION

LAYER.............................. 47

FIGURE 2-2: SERIAL VIEW OF A

TLP............................................................................................. 50

FIGURE 2-3: GENERIC TLP

FORMAT............................................................................................. 50

FIGURE 2-4: FIELDS PRESENT IN ALL

TLPS .................................................................................. 52

FIGURE 2-5: 64-BIT ADDRESS

ROUTING........................................................................................ 56

FIGURE 2-6: 32-BIT ADDRESS

ROUTING........................................................................................ 57

FIGURE 2-7: ID ROUTING WITH

4DWHEADER ............................................................................ 58

FIGURE 2-8: ID ROUTING WITH

3DWHEADER ............................................................................ 59

FIGURE 2-9: LOCATION OF BYTE ENABLES IN TLP

HEADER......................................................... 59

FIGURE 2-10: TRANSACTION

DESCRIPTOR .................................................................................... 61

FIGURE 2-11: TRANSACTION

ID.................................................................................................... 62

FIGURE 2-12: ATTRIBUTES FIELD OF TRANSACTION

DESCRIPTOR ................................................ 64

FIGURE 2-13: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF

MEMORY........................ 66

FIGURE 2-14: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF

MEMORY........................ 67

FIGURE 2-15: REQUEST HEADER FORMAT FOR I/O

TRANSACTIONS.............................................. 67

FIGURE 2-16: REQUEST HEADER FORMAT FOR CONFIGURATION

TRANSACTIONS ........................ 68

FIGURE 2-17: MESSAGE REQUEST

HEADER .................................................................................. 69

FIGURE 2-18: HEADER FOR VENDOR-DEFINED

MESSAGES ........................................................... 78

FIGURE 2-19: COMPLETION HEADER

FORMAT .............................................................................. 81

FIGURE 2-20: COMPLETER

ID ....................................................................................................... 81

FIGURE 2-21: FLOWCHART FOR HANDLING OF RECEIVED

TLPS ................................................... 83

FIGURE 2-22: FLOWCHART FOR SWITCH HANDLING OF

TLPS....................................................... 85

FIGURE 2-23: FLOWCHART FOR HANDLING OF RECEIVED

REQUEST ............................................. 90

FIGURE 2-24: VIRTUAL CHANNEL CONCEPT – AN

ILLUSTRATION .............................................. 107

FIGURE 2-25: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM

FLOW) ............. 107

FIGURE 2-26: AN EXAMPLE OF TC/VC

CONFIGURATIONS.......................................................... 110

FIGURE 2-27: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE

COMPLETER..................... 111

FIGURE 2-28: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION .....................................................................................................................

... 126

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK

LAYER ................................ 133

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE

MACHINE.................................. 135

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION

EXAMPLE.................................................... 141

FIGURE 3-4: DLLP TYPE AND CRC

FIELDS ................................................................................ 142

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND

NAK....................................... 144

FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR

INITFC1 ................................................ 144

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR

INITFC2 ................................................ 144

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR

UPDATEFC............................................ 144

FIGURE 3-9: PM DATA LINK LAYER PACKET

FORMAT ............................................................... 145

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET

FORMAT ...................................... 145

FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR

DLLPS ..................................................... 146

FIGURE 3-12: TLP WITH LCRC AND SEQUENCE NUMBER

APPLIED ........................................... 147

FIGURE 3-13: TLP FOLLOWING APPLICATION OF SEQUENCE NUMBER AND RESERVED

BITS ..... 149

FIGURE 3-14: CALCULATION OF

LCRC ...................................................................................... 151

FIGURE 3-15: RECEIVED DLLP ERROR CHECK

FLOWCHART...................................................... 157

FIGURE 3-16: ACK/NAK DLLP PROCESSING

FLOWCHART.......................................................... 158

FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF

TLPS ................................................ 162

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL

LAYER.......................................... 167

FIGURE 4-2: CHARACTER TO SYMBOL

MAPPING......................................................................... 168

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1

EXAMPLE ............................ 169

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4

EXAMPLE ............................ 169

FIGURE 4-5: TLP WITH FRAMING SYMBOLS

APPLIED ................................................................. 172

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS

APPLIED .............................................................. 173

FIGURE 4-7: FRAMED TLP ON A X1

LINK.................................................................................... 173

FIGURE 4-8: FRAMED TLP ON A X2

LINK.................................................................................... 174

FIGURE 4-9: FRAMED TLP ON A X4

LINK.................................................................................... 174

FIGURE 4-10: LFSR WITH SCRAMBLING

POLYNOMIAL............................................................... 176

FIGURE 4-11: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE

MACHINE ........ 194

FIGURE 4-12: DETECT SUBSTATE

MACHINE ............................................................................... 196

FIGURE 4-13: POLLING SUBSTATE

MACHINE .............................................................................. 201

FIGURE 4-14: CONFIGURATION SUBSTATE

MACHINE.................................................................. 214

FIGURE 4-15: RECOVERY SUBSTATE

MACHINE........................................................................... 223

FIGURE 4-16: L0S SUBSTATE

MACHINE ...................................................................................... 228

FIGURE 4-17: L1 SUBSTATE

MACHINE........................................................................................ 230

FIGURE 4-18: L2 SUBSTATE

MACHINE........................................................................................ 231

FIGURE 4-19: LOOPBACK SUBSTATE

MACHINE........................................................................... 236

FIGURE 4-20: TRANSMITTER, CHANNEL, AND RECEIVER

BOUNDARIES ...................................... 242

FIGURE 4-21: PLOT OF TRANSMITTER HPF FILTER

FUNCTIONS.................................................. 245

FIGURE 4-22: TRANSMITTER MARGINING VOLTAGE LEVELS AND

CODES .................................. 246

FIGURE 4-23: REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S

TRANSMITTER..................... 250

FIGURE 4-24: ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S

TRANSMITTER ................. 251

FIGURE 4-25: SINGLE-ENDED AND DIFFERENTIAL

LEVELS.......................................................... 252

FIGURE 4-26: FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB

DE-EMPHASIS 253

FIGURE 4-27: LOW SWING TX

PARAMETERS............................................................................... 253

FIGURE 4-28: RISE AND FALL TIME

DEFINITIONS ....................................................................... 254

FIGURE 4-29: MINIMUM PULSE WIDTH

DEFINITION ................................................................... 254

FIGURE 4-30: FULL SWING TX PARAMETERS SHOWING

DE-EMPHASIS ....................................... 255

FIGURE 4-31: MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE

DIAGRAM...... 256

FIGURE 4-32: ALGORITHM TO REMOVE DE-EMPHASIS INDUCED

JITTER..................................... 257

FIGURE 4-33: EXAMPLE OF DE-EMPHASIS JITTER

REMOVAL....................................................... 257

FIGURE 4-34: TX PACKAGE PLUS DIE RETURN LOSS

S11 ............................................................. 259

FIGURE 4-35: SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE

LOAD ..... 261

FIGURE 4-36: SETUP FOR TESTING

RECEIVER ............................................................................. 261

FIGURE 4-37: CALIBRATION CHANNEL

VALIDATION .................................................................. 264

FIGURE 4-38: CALIBRATION CHANNEL SHOWING

TMIN-PULSE...................................................... 264

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

FIGURE 4-39: CALIBRATION CHANNEL |S11| PLOT WITH TOLERANCE

LIMITS .............................. 265

FIGURE 4-40: RECEIVER RETURN LOSS MASK FOR 5.0

GT/S ..................................................... 269

FIGURE 4-41: RECEIVER EYE

MARGINS...................................................................................... 270

FIGURE 4-42: SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX

SWING.................. 271

FIGURE 4-43: EXIT FROM IDLE VOLTAGE AND TIME

MARGINS................................................... 272

FIGURE 4-44: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF

CAPACITOR............................ 277

FIGURE 4-45: BEACON,WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF

CAPACITOR........... 277

FIGURE 4-46: SIMULATION ENVIRONMENT FOR CHARACTERIZING

CHANNEL............................. 280

FIGURE 4-47: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION

RESULTS................... 283

FIGURE 4-48: MULTI-SEGMENT CHANNEL

EXAMPLE.................................................................. 284

FIGURE 4-49: COMMON REFCLK RX

ARCHITECTURE.................................................................. 286

FIGURE 4-50: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX

ARCHITECTURE287

FIGURE 4-51: DATA DRIVING

ARCHITECTURE ............................................................................ 289

FIGURE 4-52: REFCLK TEST

SETUP ............................................................................................. 291

FIGURE 4-53: SEPARATE REFCLK

ARCHITECTURE ...................................................................... 292

FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW

DIAGRAM ............................................. 297

FIGURE 5-2: ENTRY INTO THE L1 LINK

STATE............................................................................ 304

FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM

COMPONENT........................ 307

FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE#

ROUTING. 310

FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE

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