PCIe协议3.1：DPC功能与可靠性提升

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"PCIe协议3.1是PCI Express Base Specification的一个版本，相较于3.0，引入了DPC（Disruptive Power Change）能力，旨在提高系统的可靠性和支持NVMe设备的热插拔操作。这一版本发布于2015年12月7日，是对先前版本的修订和增强。" PCIe协议3.1是计算机系统中广泛使用的高速接口标准，它定义了设备间数据传输的规范，以实现高效、低延迟的数据交换。在3.1版本中，主要的改进点之一是增加了DPC（Disruptive Power Change）功能，这是针对NVMe设备设计的一项新特性。NVMe（Non-Volatile Memory express）是一种高性能的存储协议，适用于固态硬盘（SSD），尤其是企业级应用。DPC能力允许系统在不造成破坏性电源变化的情况下，安全地进行NVMe设备的热插拔操作，提升了系统的稳定性和用户友好性。 PCIe协议的历史演变也值得关注。从1.0到3.1，每次迭代都伴随着数据速率的提升和错误处理机制的完善。例如，1.0版本首次发布时，数据速率是2.5GT/s；2.0版本将数据速率翻倍至5.0GT/s，并且添加了错误报告和工程变更通知（ECN）来改进系统性能。到了3.0版本，数据传输速度进一步提升，同时继续优化错误处理和兼容性。3.1a则是在3.1基础上的小幅修订，包含了对已知问题的修复和新特性的集成。在PCIe 3.1的众多ECN中，包括了内部错误报告、多播、原子操作、可调整大小的BAR（Base Address Register）、动态功率分配、基于ID的排序、延迟容忍报告、替代路由-ID解释（ARI）、扩展标签使能默认、TLP处理提示和TLP前缀等。这些ECN的实施增强了系统的功能，提升了效率，同时也增强了设备间的通信可靠性。 PCIe协议3.1通过引入DPC功能和一系列的ECN，不仅提高了数据传输速度，还增强了系统稳定性，特别是对于NVMe存储设备的支持，使得数据中心和高性能计算环境能够更灵活、更可靠地管理硬件资源。

PCI EXPRESS BASE SPECIFICATION, REV. 3.1a

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 49

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 50

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 54

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 56

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 57

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 62

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 65

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 66

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 67

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 68

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 73

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 75

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 75

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 77

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 78

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 79

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 81

FIGURE 2-13: TRANSACTION ID .................................................................................................... 82

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 84

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 88

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 88

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 89

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 90

FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 91

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 91

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 92

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 93

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 93

FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 95

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 105

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 106

FIGURE 2-27: LN MESSAGE ......................................................................................................... 108

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 109

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 111

FIGURE 2-30: LTR MESSAGE ...................................................................................................... 112

FIGURE 2-31: OBFF MESSAGE ................................................................................................... 113

FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 114

FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 115

FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 116

FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 117

FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 117

FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 124

FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 126

PCI EXPRESS BASE SPECIFICATION, REV. 3.1a

FIGURE 2-39: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 131

FIGURE 2-40: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 148

FIGURE 2-41: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 148

FIGURE 2-42: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 151

FIGURE 2-43: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 152

FIGURE 2-44: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION ........................................................................................................................ 167

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 175

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 178

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED

FRAMING ............................................................................................................................. 183

FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 184

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 186

FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 186

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 186

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 187

FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 187

FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 187

FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 188

FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 189

FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS

............................................................................................................................................. 191

FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 193

FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 201

FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 202

FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 206

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 211

FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 212

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 213

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 213

FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 216

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 217

FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 217

FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 218

FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 218

FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL ............................................................... 220

FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A

BLOCK ................................................................................................................................. 221

FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 221

FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 225

FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 227

FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 227

FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 228

FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 228

FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 235

FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 237

PCI EXPRESS BASE SPECIFICATION, REV. 3.1a

FIGURE 4-20: EQUALIZATION FLOW............................................................................................ 243

FIGURE 4-21: ELECTRICAL IDLE EXIT ORDERED SET FOR 8.0 GT/S AND ABOVE DATA RATES ... 254

FIGURE 4-22: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 269

FIGURE 4-23: DETECT SUBSTATE MACHINE ............................................................................... 271

FIGURE 4-24: POLLING SUBSTATE MACHINE .............................................................................. 279

FIGURE 4-25: CONFIGURATION SUBSTATE MACHINE .................................................................. 294

FIGURE 4-26: RECOVERY SUBSTATE MACHINE ........................................................................... 315

FIGURE 4-27: L0S SUBSTATE MACHINE ...................................................................................... 322

FIGURE 4-28: L1 SUBSTATE MACHINE ........................................................................................ 324

FIGURE 4-29: L2 SUBSTATE MACHINE ........................................................................................ 326

FIGURE 4-30: LOOPBACK SUBSTATE MACHINE ........................................................................... 331

FIGURE 4-31: TRANSMITTER, CHANNEL, AND RECEIVER BOUNDARIES ...................................... 345

FIGURE 4-32: REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S TRANSMITTER ..................... 346

FIGURE 4-33: ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S TRANSMITTER ................. 346

FIGURE 4-34: TX TEST BOARD EXAMPLE .................................................................................... 347

FIGURE 4-35: SINGLE-ENDED AND DIFFERENTIAL LEVELS .......................................................... 349

FIGURE 4-36: FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB DE-EMPHASIS 350

FIGURE 4-37: REDUCED SWING TX PARAMETERS ....................................................................... 350

FIGURE 4-38: MINIMUM PULSE WIDTH DEFINITION ................................................................... 351

FIGURE 4-39: FULL SWING TX PARAMETERS SHOWING DE-EMPHASIS ....................................... 352

FIGURE 4-40: MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE DIAGRAM ...... 353

FIGURE 4-41: TX EQUALIZATION FIR REPRESENTATION ............................................................ 355

FIGURE 4-42: DEFINITION OF TX VOLTAGE LEVELS AND EQUALIZATION RATIOS ...................... 356

FIGURE 4-43: WAVEFORM MEASUREMENT POINTS FOR PRE-SHOOT AND DE-EMPHASIS ............ 357

FIGURE 4-44: V

TX-FS-NO-EQ

MEASUREMENT ................................................................................ 360

FIGURE 4-45: TXEQ COEFFICIENT SPACE TRIANGULAR MATRIX EXAMPLE ............................... 361

FIGURE 4-46: MEASURING V

TX-EIEOS-FS

AND V

TX-EIEOS-RS

........................................................... 362

FIGURE 4-47: COMPLIANCE PATTERN AND RESULTING PACKAGE LOSS TEST WAVEFORM ........ 363

FIGURE 4-48: TRANSMITTER MARGINING VOLTAGE LEVELS AND CODES .................................. 364

FIGURE 4-49: PLOT OF TRANSMITTER HPF FILTER FUNCTIONS .................................................. 366

FIGURE 4-50: ALGORITHM TO REMOVE DE-EMPHASIS INDUCED JITTER ..................................... 367

FIGURE 4-51: EXAMPLE OF DE-EMPHASIS JITTER REMOVAL ....................................................... 368

FIGURE 4-52: RELATION BETWEEN DATA EDGE PDFS AND RECOVERED DATA CLOCK ............. 370

FIGURE 4-53: DERIVATION OF T

TX-UTJ

AND T

TX-UDJDD

................................................................ 370

FIGURE 4-54: PWJ RELATIVE TO CONSECUTIVE EDGES 1 UI APART .......................................... 371

FIGURE 4-55: DEFINITION OF T

TX-UPW-DJDD

AND T

TX-UPW-TJ

........................................................ 372

FIGURE 4-56: TX, RX DIFFERENTIAL RETURN LOSS MASK ......................................................... 372

FIGURE 4-57: TX, RX COMMON MODE RETURN LOSS MASK ...................................................... 373

FIGURE 4-58: CALIBRATION CHANNEL VALIDATION .................................................................. 380

FIGURE 4-59: CALIBRATION CHANNEL SHOWING T

MIN-PULSE

...................................................... 380

FIGURE 4-60: CALIBRATION CHANNEL |S

| PLOT WITH TOLERANCE LIMITS .............................. 381

FIGURE 4-61: SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE LOAD ..... 381

FIGURE 4-62: SETUP FOR TESTING RECEIVER ............................................................................. 382

FIGURE 4-63: RECEIVER EYE MARGINS ...................................................................................... 385

FIGURE 4-64: SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX SWING .................. 386

FIGURE 4-65: RX TESTBOARD TOPOLOGY ................................................................................... 387

PCI EXPRESS BASE SPECIFICATION, REV. 3.1a

FIGURE 4-66: INSERTION LOSS GUIDELINES FOR CALIBRATION/BREAKOUT CHANNELS ............. 388

FIGURE 4-67: BEHAVIORAL CDR MODEL FOR RX MEASUREMENT ............................................ 389

FIGURE 4-68: TRANSFER FUNCTION FOR BEHAVIORAL CTLE .................................................... 390

FIGURE 4-69: LOSS CURVES FOR BEHAVIORAL CTLE ................................................................ 390

FIGURE 4-70: EQUATION AND FLOW DIAGRAM FOR 1-TAP DFE ................................................. 391

FIGURE 4-71: SETUP FOR CALIBRATING THE STRESSED VOLTAGE EYE ...................................... 392

FIGURE 4-72: LAYOUT FOR STRESSED VOLTAGE TESTING OF RECEIVER .................................... 394

FIGURE 4-73: LAYOUT FOR CALIBRATING THE STRESSED JITTER EYE ........................................ 395

FIGURE 4-74: SWEPT SJ MASK .................................................................................................... 396

FIGURE 4-75: LAYOUT FOR JITTER TESTING COMMON REFCLK RX ............................................ 397

FIGURE 4-76: LAYOUT FOR JITTER TESTING DATA CLOCKED REFCLK RX .................................. 397

FIGURE 4-77: SWEPT SJ MASK .................................................................................................... 399

FIGURE 4-78: EXIT FROM IDLE VOLTAGE AND TIME MARGINS ................................................... 403

FIGURE 4-79: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF CAPACITOR ............................ 408

FIGURE 4-80: BEACON, WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF CAPACITOR ........... 408

FIGURE 4-81: SIMULATION ENVIRONMENT FOR CHARACTERIZING CHANNEL ............................. 410

FIGURE 4-82: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION RESULTS ................... 414

FIGURE 4-83: MULTI-SEGMENT CHANNEL EXAMPLE .................................................................. 415

FIGURE 4-84: FLOW DIAGRAM FOR CHANNEL TOLERANCING ..................................................... 416

FIGURE 4-85: TX/RX BEHAVIORAL PACKAGE MODELS .............................................................. 417

FIGURE 4-86: BEHAVIORAL TX AND RX S-PARAMETER FILE DETAILS ....................................... 417

FIGURE 4-87: DERIVATION OF JITTER PARAMETERS IN TABLE 4-26 ............................................ 420

FIGURE 4-88: EH, EW MASK ...................................................................................................... 420

FIGURE 4-89: REFCLK TEST SETUP ............................................................................................. 423

FIGURE 4-90: LIMITS FOR PHASE JITTER FROM THE REFERENCE CLOCK ...................................... 424

FIGURE 4-91: COMMON REFCLK RX ARCHITECTURE .................................................................. 425

FIGURE 4-92: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX ARCHITECTURE 426

FIGURE 4-93: DATA CLOCKED RX ARCHITECTURE ..................................................................... 428

FIGURE 4-94: SEPARATE REFCLK WITH NO SSC (SRNS) ARCHITECTURE ................................. 430

FIGURE 4-95: SEPARATE REFCLK WITH INDEPENDENT SSC ARCHITECTURE .............................. 431

FIGURE 4-96: INFORMATIVE CDR JITTER TRANSFER FUNCTION FOR THE SEPARATE REFCLK WITH

INDEPENDENT SSC (SRIS) ARCHITECTURE AT 5.0 GT/S ..................................................... 432

FIGURE 4-97: 8.0 GT/S COMMON REFCLK RX ARCHITECTURE WITH ω

, ζ LIMITS ..................... 435

FIGURE 4-98: 8.0 GT/S DATA CLOCKED RX ARCHITECTURE WITH ω

, ζ LIMITS ........................ 437

FIGURE 4-99: INFORMATIVE CDR JITTER TRANSFER FUNCTION FOR THE SEPARATE REFCLK WITH

INDEPENDENT SSC (SRIS) ARCHITECTURE AT 8.0 GT/S ..................................................... 439

FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 445

FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 453

FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT ........................ 456

FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING . 459

FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE .................................................. 463

FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED) ................ 476

FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 477

FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 479

FIGURE 5-9: STATE DIAGRAM FOR L1 PM SUBSTATES ................................................................ 485

FIGURE 5-10: DOWNSTREAM PORT WITH A SINGLE PLL ............................................................. 486

PCI EXPRESS BASE SPECIFICATION, REV. 3.1a

FIGURE 5-11: MULTIPLE DOWNSTREAM PORTS WITH A SHARED PLL ......................................... 487

FIGURE 5-12: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 489

FIGURE 5-13: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 490

FIGURE 5-14: L1.2 SUBSTATES .................................................................................................... 491

FIGURE 5-15: EXAMPLE: ILLUSTRATION OF BOUNDARY CONDITION DUE TO DIFFERENT SAMPLING

CLKREQ# ...................................................................................................................... 492

FIGURE 5-16: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 494

FIGURE 5-17: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 494

FIGURE 6-1: ERROR CLASSIFICATION .......................................................................................... 504

FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING

OPERATIONS ........................................................................................................................ 521

FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 522

FIGURE 6-4: TC FILTERING EXAMPLE ......................................................................................... 542

FIGURE 6-5: TC TO VC MAPPING EXAMPLE ............................................................................... 543

FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS .................. 544

FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH ................ 545

FIGURE 6-8: SWITCH ARBITRATION STRUCTURE ......................................................................... 546

FIGURE 6-9: VC ID AND PRIORITY ORDER – AN EXAMPLE ......................................................... 547

FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL .............................................................. 550

FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 584

FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS ................................ 585

FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES ............................................... 599

FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE ......................................... 600

FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES ................................................... 618

FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 622

FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT .................................................. 623

FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS ...................................................... 625

FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY

MESSAGES ........................................................................................................................... 626

FIGURE 6-20. PASID TLP PREFIX: ....................................................................................... 629

FIGURE 6-21: SAMPLE SYSTEM BLOCK DIAGRAM ....................................................................... 633

FIGURE 6-22: LN PROTOCOL BASIC OPERATION ......................................................................... 634

FIGURE 6-23: EXAMPLE SYSTEM TOPOLOGIES USING PTM ......................................................... 640

FIGURE 6-24: PRECISION TIME MEASUREMENT LINK PROTOCOL ................................................ 641

FIGURE 6-25: PRECISION TIME MEASUREMENT EXAMPLE ........................................................... 643

FIGURE 6-26: PTM REQUESTER OPERATION ............................................................................... 646

FIGURE 6-27: PTM TIMESTAMP CAPTURE EXAMPLE ................................................................... 649

FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 654

FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 654

FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 655

FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER ............................................................ 666

FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER ................................................................ 673

FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER ................................................................ 675

FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ..................................................... 679

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