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首页Intel PCIe千兆网卡驱动开发手册
"Intel千兆网卡开发手册是针对基于PCI Express(PCIe)的千兆以太网控制器的开源软件开发者的重要参考资料。手册涵盖了82571EB、82572EI、82573E、82573V以及82563EB等型号的Intel网卡,同时也提及了e1000和e1000e这两个知名的Intel网卡驱动系列。这份文档旨在帮助开发者理解和构建针对这些硬件的驱动程序。"
在Intel的千兆网卡开发手册中,开发者可以找到以下关键知识点:
1. **PCIe技术**:PCI Express是现代计算机中用于高速数据传输的接口标准,提供了比传统PCI更高的带宽。手册会详细介绍如何与PCIe总线通信,包括配置空间的访问、中断处理和DMA(直接内存访问)操作。
2. **82571E/82572E/82573E等系列网卡**:这些是Intel生产的千兆以太网控制器,每种型号都有其特定的功能和特性。手册将涵盖这些硬件的内部结构、寄存器布局以及如何与它们进行低级交互。
3. **e1000和e1000e驱动**:e1000是Intel早期的千兆以太网控制器驱动,而e1000e是其后续版本,支持更多的功能和改进的性能。手册将深入解析这两个驱动系列的实现细节,包括初始化流程、中断处理、数据包收发机制等。
4. **软件开发流程**:手册将指导开发者如何编写和调试驱动程序,包括必要的设备注册、网络协议栈的集成、错误处理和性能优化等方面。
5. **硬件接口**:介绍与网卡相关的物理层(PHY)和媒体访问控制层(MAC)接口,以及如何进行链路状态管理、速度和双工设置。
6. **中断处理**:详细讲解中断请求(IRQ)的管理和中断联合(Interrupt Coalescing)技术,以降低处理器中断负担并提高系统效率。
7. **DMA操作**:DMA是网卡进行数据传输的主要方式,手册会解释如何设置DMA引擎,以及如何安全高效地进行数据缓冲和交换。
8. **电源管理**:Intel网卡支持各种电源管理模式,手册将阐述如何在不同电源状态下正确操作设备,以实现节能目标。
9. **兼容性和认证**:对于操作系统(如Linux或Windows)的兼容性,以及如何通过网络标准的认证,如IEEE 802.3ab(千兆以太网)。
10. **法律声明**:Intel明确指出,提供此文档并不授予任何知识产权许可,并且产品不适用于可能导致人身伤害或死亡的应用。
手册中的内容不仅限于上述点,还包括了最新的修订版(Revision 2.4)所做的变更,以及可能的未来更新。对任何想要深入理解Intel千兆网卡驱动开发的人来说,这是一份非常宝贵的资源。
xiv
Contents
13.3.8.68 82563EB/82564EB Page Register (Any Page, Register 22) .....................357
13.3.8.69 82563EB/82564EB Alternate Page Register (Any Page, Register 29)......357
13.3.8.70 82563EB/82564EB GLCI
Mode Control Register (Page 193, Register 16)........................................358
13.3.9 PHY Address and Page Register (82563EB/82564EB) ..........................................358
13.3.10 SERDES ANA (82571EB/82572EI).........................................................................359
13.3.11 Flow Control Address Low.......................................................................................359
13.3.12 Flow Control Address High......................................................................................360
13.3.13 Flow Control Type....................................................................................................360
13.3.14 GLCI Control and Status Registers (631xESB/632xESB).......................................360
13.3.15 VLAN Ether Type.....................................................................................................362
13.3.16 MDC/MDIO PHY Address Register (631xESB/632xESB).......................................362
13.3.17 ULT Fuse Register 3 (82573E/82573V/82573L) .....................................................363
13.3.18 Flow Control Transmit Timer Value .........................................................................363
13.3.19 Transmit Configuration Word Register ....................................................................364
13.3.20 Receive Configuration Word Register .....................................................................366
13.3.21 LED Control .............................................................................................................369
13.3.21.1 MODE Encodings for LED Outputs............................................................370
13.3.22 Extended Configuration Control (82573E/82573V/82573L) ....................................372
13.3.23 Extended Configuration Size (82573E/82573V/82573L)......................................... 372
13.3.24 Packet Buffer Allocation...........................................................................................373
13.3.25 MNG EEPROM Control Register (82571EB and 82573E/82573V/82573L)............373
13.3.26 Software/Firmware Synchronization (631xESB/632xESB)...................................... 374
13.3.27 Interrupt Cause Read Register................................................................................376
13.3.28 Interrupt Throttling Rate........................................................................................... 379
13.3.29 Interrupt Cause Set Register ...................................................................................380
13.3.30 Interrupt Mask Set/Read Register ...........................................................................382
13.3.31 Interrupt Mask Clear Register..................................................................................383
13.3.32 Interrupt Acknowledge Auto Mask Register.............................................................384
13.3.33 Receive Control Register.........................................................................................384
13.3.34 Early Receive Threshold (82573E/82573V/82573L) ...............................................389
13.3.35 Flow Control Receive Threshold Low...................................................................... 390
13.3.36 Flow Control Receive Threshold High .....................................................................391
13.3.37 Packet Split Receive Control Register.....................................................................392
13.3.38 Receive Descriptor Base Address Low Queue 0.....................................................393
13.3.39 Receive Descriptor Base Address High Queue 0....................................................393
13.3.40 Receive Descriptor Length Queue 0........................................................................394
13.3.41 Receive Descriptor Head Queue 0..........................................................................394
13.3.42 Receive Descriptor Tail Queue 0.............................................................................395
13.3.43 Receive Interrupt Delay Timer (Packet Timer) Register..........................................395
13.3.44 Receive Descriptor Control......................................................................................396
13.3.45 Receive Interrupt Absolute Delay Timer..................................................................397
13.3.46 Receive Descriptor Base Address Low Queue 1.....................................................398
13.3.47 Receive Descriptor Base Address High Queue 1....................................................398
13.3.48 Receive Descriptor Length Queue 1........................................................................399
13.3.49 Receive Descriptor Head Queue 1..........................................................................399
13.3.50 Receive Descriptor Tail Queue 1.............................................................................400
13.3.51 Receive Descriptor Control 1...................................................................................400
13.3.52 Receive Small Packet Detect Interrupt....................................................................402
13.3.53 Receive ACK Interrupt Delay Register ....................................................................402
xv
Contents
13.3.54 CPU Vector Register ...............................................................................................403
13.3.55 Receive Checksum Control .....................................................................................403
13.3.56 Receive Filter Control Register................................................................................404
13.3.57 Transmit Control Register........................................................................................405
13.3.58 Transmit Control Extended (631xESB/632xESB)....................................................407
13.3.59 Transmit IPG Register .............................................................................................408
13.3.60 Adaptive IFS Throttle Register.................................................................................409
13.3.61 Transmit Descriptor Base Address Low ..................................................................410
13.3.62 Transmit Descriptor Base Address High..................................................................410
13.3.63 Transmit Descriptor Length .....................................................................................411
13.3.64 Transmit Descriptor Head........................................................................................411
13.3.65 Transmit Descriptor Tail...........................................................................................412
13.3.66 Transmit Interrupt Delay Value ................................................................................412
13.3.67 Transmit Descriptor Control.....................................................................................413
13.3.68 Transmit Absolute Interrupt Delay Value .................................................................415
13.3.69 Transmit Arbitration Counter Queue 0.....................................................................416
13.3.69.1 Multiple Queues Limitations .......................................................................416
13.3.70 Transmit Descriptor Base Address Low Queue 1....................................................418
13.3.71 Transmit Descriptor Base Address High Queue 1...................................................419
13.3.72 Transmit Descriptor Length Queue 1.......................................................................419
13.3.73 Transmit Descriptor Head Queue 1 .........................................................................419
13.3.74 Transmit Descriptor Tail Queue 1............................................................................420
13.3.75 Transmit Descriptor Control 1..................................................................................420
13.3.76 Transmit Arbitration Counter Queue 1.....................................................................423
13.4 Filter Registers..........................................................................................................................424
13.4.1 Multicast Table Array ...............................................................................................424
13.4.2 Receive Address Low ..............................................................................................426
13.4.3 Receive Address High .............................................................................................426
13.4.4 VLAN Filter Table Array...........................................................................................427
13.4.5 Multiple Receive Queues Command Register.........................................................428
13.4.6 RSS Interrupt Mask Register...................................................................................429
13.4.7 RSS Interrupt Request Register ..............................................................................429
13.4.8 Redirection Table.....................................................................................................430
13.4.9 RSS Random Key Register .....................................................................................430
13.5 Wakeup Registers ....................................................................................................................430
13.5.1 Wakeup Control Register.........................................................................................430
13.5.2 Wakeup Filter Control Register................................................................................431
13.5.3 Wakeup Status Register ..........................................................................................432
13.5.4 IP Address Valid ......................................................................................................433
13.5.5 IPv4 Address Table .................................................................................................433
13.5.6 IPv6 Address Table .................................................................................................434
13.5.7 Wakeup Packet Length............................................................................................435
13.5.8 Wakeup Packet Memory (128 Bytes) ......................................................................435
13.5.9 Flexible Filter Length Table .....................................................................................436
13.5.10 Flexible Filter Mask Table........................................................................................437
13.5.11 Flexible Filter Value Table .......................................................................................438
13.6 MNG Register (82571EB).........................................................................................................438
13.6.1 Management Control Register.................................................................................438
13.7 PB ECC Register (82571EB)....................................................................................................441
xvi
Contents
13.8 PCIe* Registers ........................................................................................................................ 442
13.8.1 PCIe* Control...........................................................................................................442
13.8.2 PCIe* Statistics Control #1 ......................................................................................444
13.8.3 PCIe* Statistics Control #2 ......................................................................................445
13.8.4 PCIe* Statistics Control #3 ......................................................................................449
13.8.5 PCIe* Statistics Control #4 ......................................................................................450
13.8.6 PCIe* Counter #0.....................................................................................................451
13.8.7 PCIe* Counter #1.....................................................................................................451
13.8.8 PCIe* Counter #2.....................................................................................................451
13.8.9 PCIe* Counter #3.....................................................................................................451
13.8.10 Function Active and Power State to MNG ...............................................................451
13.8.11 SerDes/CCM/PCIe* CSR (82571EB/82572EI)........................................................454
13.8.12 SerDes/CCM/PCIe* CSR (82571EB/82572EI)........................................................454
13.8.13 SerDes/CCM/PCIe* CSR (82571EB/82572EI)........................................................456
13.8.14 SerDes/CCM/PCIe* CSR (82571EB/82572EI)........................................................456
13.8.15 Analog Control Register (631xESB/632xESB) ........................................................456
13.8.16 SerDes/CCM/PCIe* CSR (82571EB/82572EI)........................................................457
13.8.17 Software Semaphore Register.................................................................................458
13.8.18 Firmware Semaphore Register................................................................................459
13.9 Statistics Registers ...................................................................................................................460
13.9.1 CRC Error Count .....................................................................................................460
13.9.2 Alignment Error Count ............................................................................................. 461
13.9.3 Symbol Error Count .................................................................................................461
13.9.4 RX Error Count ........................................................................................................461
13.9.5 Missed Packets Count.............................................................................................462
13.9.6 Single Collision Count..............................................................................................462
13.9.7 Excessive Collisions Count......................................................................................463
13.9.8 Multiple Collision Count ...........................................................................................463
13.9.9 Late Collisions Count...............................................................................................463
13.9.10 Collision Count.........................................................................................................464
13.9.11 Defer Count .............................................................................................................464
13.9.12 Transmit with No CRS .............................................................................................465
13.9.13 Sequence Error Count............................................................................................. 465
13.9.14 Carrier Extension Error Count (631xESB/632xESB)...............................................466
13.9.15 Receive Length Error Count ....................................................................................466
13.9.16 XON Received Count ..............................................................................................467
13.9.17 XON Transmitted Count ..........................................................................................467
13.9.18 XOFF Received Count.............................................................................................468
13.9.19 XOFF Transmitted Count.........................................................................................468
13.9.20 FC Received Unsupported Count............................................................................469
13.9.21 Packets Received (64 Bytes) Count........................................................................469
13.9.22 Packets Received (65-127 Bytes) Count.................................................................469
13.9.23 Packets Received (128-255 Bytes) Count............................................................... 470
13.9.24 Packets Received (256-511 Bytes) Count............................................................... 470
13.9.25 Packets Received (512-1023 Bytes) Count............................................................. 471
13.9.26 Packets Received (1024 to Max Bytes) Count ........................................................471
13.9.27 Good Packets Received Count................................................................................471
13.9.28 Broadcast Packets Received Count ........................................................................472
13.9.29 Multicast Packets Received Count ..........................................................................472
13.9.30 Good Packets Transmitted Count............................................................................473
xvii
Contents
13.9.31 Good Octets Received Count ..................................................................................473
13.9.32 Good Octets Transmitted Count ..............................................................................474
13.9.33 Receive No Buffers Count .......................................................................................474
13.9.34 Receive Undersize Count ........................................................................................475
13.9.35 Receive Fragment Count.........................................................................................475
13.9.36 Receive Oversize Count ..........................................................................................475
13.9.37 Receive Jabber Count .............................................................................................476
13.9.38 Management Packets Received Count ...................................................................476
13.9.39 Management Packets Dropped Count.....................................................................476
13.9.40 Management Packets Transmitted Count ...............................................................477
13.9.41 Total Octets Received .............................................................................................477
13.9.42 Total Octets Transmitted .........................................................................................477
13.9.43 Total Packets Received ...........................................................................................478
13.9.44 Total Packets Transmitted .......................................................................................478
13.9.45 Packets Transmitted (64 Bytes) Count ....................................................................479
13.9.46 Packets Transmitted (65-127 Bytes) Count.............................................................479
13.9.47 Packets Transmitted (128-255 Bytes) Count...........................................................479
13.9.48 Packets Transmitted (256-511 Bytes) Count...........................................................480
13.9.49 Packets Transmitted (512-1023 Bytes) Count.........................................................480
13.9.50 Packets Transmitted (1024 Bytes or Greater) Count...............................................481
13.9.51 Multicast Packets Transmitted Count ......................................................................481
13.9.52 Broadcast Packets Transmitted Count ....................................................................481
13.9.53 TCP Segmentation Context Transmitted Count ......................................................482
13.9.54 TCP Segmentation Context Tx Fail Count...............................................................482
13.9.55 Interrupt Assertion Count.........................................................................................483
13.9.56 Interrupt Cause Rx Packet Timer Expire Count.......................................................483
13.9.57 Interrupt Cause Rx Absolute Timer Expire Count....................................................483
13.9.58 Interrupt Cause Tx Packet Timer Expire Count .......................................................483
13.9.59 Interrupt Cause Tx Absolute Timer Expire Count ....................................................484
13.9.60 Interrupt Cause Transmit Queue Empty Count .......................................................484
13.9.61 Interrupt Cause Transmit Descriptor Low Threshold Count ....................................485
13.9.62 Interrupt Cause Receive Descriptor Minimum Threshold Count .............................485
13.9.63 Interrupt Cause Receive Overrun Count .................................................................485
14 General Initialization and Reset Operation..................................................487
14.1 Introduction...............................................................................................................................487
14.2 Power Up State.........................................................................................................................487
14.3 Initialization Sequence..............................................................................................................487
14.4 Interrupts During Initialization ...................................................................................................488
14.5 Global Reset and General Configuration..................................................................................488
14.6 Receive Initialization.................................................................................................................490
14.6.1 Initialize the Receive Control Register.....................................................................490
14.7 Transmit Initialization................................................................................................................490
14.8 Link Setup Mechanisms and Control/Status Bit Summary .......................................................491
14.8.1 PHY Initialization......................................................................................................491
14.8.2 MAC/PHY Link Setup ..............................................................................................492
14.8.3 MAC/SerDes (TBI-Mode) Link Setup.......................................................................496
14.9 Reset Operation........................................................................................................................497
14.10 Initialization of Statistics............................................................................................................500
xviii
Contents
15 Diagnostics and Testability ...............................................................................501
15.1 Diagnostics ............................................................................................................................... 501
15.1.1 FIFO Pointer Accessibility........................................................................................501
15.1.2 FIFO Data Accessibility ...........................................................................................501
15.1.3 Loopback Operations............................................................................................... 502
15.2 Testability .................................................................................................................................502
15.2.1 EXTEST Instruction .................................................................................................502
15.2.2 SAMPLE/PRELOAD Instruction .............................................................................. 502
15.2.3 IDCODE Instruction .................................................................................................502
15.2.4 BYPASS Instruction.................................................................................................502
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