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首页Intel X550系列以太网控制器数据表
"Intel X550系列网络控制器是一款高性能的以太网解决方案,集成了10GbE、1GbE和100Mb/s的铜缆PHYs,适用于各种网络环境。产品规格书中详细列出了该控制器的多种功能特性,包括硬件配置、网络性能优化、中断处理机制以及流量管理等。"
Intel Ethernet Controller X550是Intel Ethernet Products Group (EPG)推出的一款网络控制器,其主要特点包括:
1. **硬件特性**:
- **串行闪存接口**:用于存储设备配置和固件。
- **可配置的LED操作**:允许软件控制或自定义OEM LED显示,提供灵活的指示灯功能。
- **设备禁用能力**:可通过软件禁用控制器,便于系统管理。
- 提供两种封装尺寸:25mmx25mm(X550-BT2)和17mmx17mm(X550-AT2),适应不同空间需求。
2. **网络性能**:
- **集成的PHYs**:支持10 Gigabit Ethernet(10GbE)、1 Gigabit Ethernet(1GbE)和100 Megabit Ethernet(100Mb/s)连接。
- **大帧支持**:最大可支持15.5KB的Jumbo帧,提高数据传输效率。
- **流量控制**:支持发送/接收暂停帧和接收FIFO阈值,确保网络稳定性。
- **统计信息**:提供管理与RMON(远程网络监控)所需的统计功能,便于故障排查和性能分析。
- **802.1q VLAN支持**:增强网络隔离和管理能力。
3. **智能卸载功能**:
- **TCP段卸载**:最大可卸载256KB,减轻CPU负担。
- **IPv6支持**:包括IP/TCP和IP/UDP接收校验和卸载,提高处理速度。
- **碎片UDP校验和卸载**:用于分组重组,优化网络效率。
4. **中断处理**:
- **Message Signaled Interrupts (MSI)**:高效的数据传输中断机制。
- **MSI-X**:扩展的MSI,支持更多的中断向量,进一步提升性能。
- **中断节流控制**:限制最大中断速率,改善CPU利用率。
- **动态中断调制**:根据网络活动自动调整中断频率。
- **TCP定时器中断**:优化TCP连接管理。
5. **流量管理和优化**:
- **Flow Director**:提供16x8和32x4的流导演示,实现高效的数据包定向。
- **128个发送队列**:增强并发处理能力,提高网络吞吐量。
- **接收包头拆分**和**接收头复制**:优化数据处理流程。
- **放松排序(Relaxed Ordering)**:在网络层提供更灵活的数据包顺序处理。
Intel Ethernet Controller X550是一款功能强大的网络控制器,其丰富的特性使得它在数据中心、服务器和企业网络环境中能够提供高效、可靠且可定制化的网络服务。通过硬件加速和智能卸载技术,可以显著降低CPU负载,提高整体系统性能。
Intel
®
Ethernet Controller X550 Datasheet
Contents
16 333369-007
6.2.23.3 Word2 (0x0002) ...................................................................................................... 347
6.2.23.4 Word3 (0x0003) ...................................................................................................... 347
6.2.23.5 Word4 (0x0004) ...................................................................................................... 347
6.2.23.6 Word5 (0x0005) ...................................................................................................... 348
6.2.24 Mini Loader Module Section .............................................................................................. 349
6.2.24.1 Mini Loader Section Header (0x0000).......................................................................... 349
6.2.24.2 Mini Loader Code (0x0001)........................................................................................ 349
6.2.24.3 Mini Loader Section Footer (0x0002)........................................................................... 349
6.2.25 PHY Config Section.......................................................................................................... 350
6.2.25.1 Section Length (0x0000)........................................................................................... 350
6.2.25.2 PMA RX Prov Port0 LSA (0x0001) ............................................................................... 350
6.2.25.3 PMA RX Prov Port0 MSA (0x0002) .............................................................................. 351
6.2.25.4 PMA RX Prov Port0 Data (0x0003) .............................................................................. 351
6.2.25.5 PMA RX Prov Port0 Field Enables (0x0004) .................................................................. 351
6.2.25.6 PMA RX Prov Port1 LSA (0x0005) ............................................................................... 351
6.2.25.7 PMA RX Prov Port1 MSA (0x0006) .............................................................................. 352
6.2.25.8 PMA RX Prov Port1 Data (0x0007) .............................................................................. 352
6.2.25.9 PMA RX Prov Port1 Field Enables (0x0008) .................................................................. 352
6.2.25.10 Glob Interrupt Vendor Mask LSA (0x0009)................................................................... 352
6.2.25.11 Glob Interrupt Vendor Mask MSA (0x000A).................................................................. 353
6.2.25.12 Glob Interrupt Vendor Mask Data (0x000B) ................................................................. 353
6.2.25.13 Glob Interrupt Vendor Mask Field Enables (0x000C)...................................................... 353
6.2.25.14 Glob Interrupt Standard Mask LSA (0x000D)................................................................ 354
6.2.25.15 Glob Interrupt Standard Mask MSA (0x000E) ............................................................... 354
6.2.25.16 Glob Interrupt Standard Mask Data (0x000F)............................................................... 354
6.2.25.17 Glob Interrupt Standard Mask Field Enables (0x0010) ................................................... 355
6.2.25.18 CSR RAW1 (0x0011)................................................................................................. 355
6.2.25.19 Section Footer (0x0012) ........................................................................................... 355
6.2.26 PCIe Link (LCB) Configuration Section................................................................................ 356
6.2.26.1 Section Length (0x0000)........................................................................................... 356
6.2.26.2 Reg Write Indirect List (0x0001) ................................................................................ 356
6.2.27 PCIe Analog Configuration Module Section.......................................................................... 356
6.2.27.1 Section Length (0x0000)........................................................................................... 356
6.2.27.2 PCI PHY FW (0x0001) ............................................................................................... 356
6.2.28 2'nd Init Module Section................................................................................................... 357
6.2.28.1 Data (0x2000) ......................................................................................................... 357
6.2.29 FCoE Scratch Pad Section................................................................................................. 357
6.2.29.1 Reserved (0x0000)................................................................................................... 357
6.2.30 Firmware Module Section ................................................................................................. 358
6.2.30.1 FW 2M (0x0000) ...................................................................................................... 358
6.2.31 PXE/OROM Module Section ............................................................................................... 358
6.2.31.1 OROM 2M (0x0000).................................................................................................. 358
6.2.32 AQ PHY Module Section.................................................................................................... 359
6.2.32.1 PHY 2M (0x0000) ..................................................................................................... 359
6.2.33 Free Provisioning Module Section....................................................................................... 359
6.2.33.1 Reserved (0x0000)................................................................................................... 359
Chapter 7 Inline Functions ........................................................................................... 361
7.1 Receive Functionality ............................................................................................................. 361
7.1.1 MAC Layer - Receive........................................................................................................ 361
7.1.1.1 Packet Acceptance Criteria ........................................................................................ 361
7.1.1.2 CRC Strip ................................................................................................................ 362
7.1.2 Packet Filtering............................................................................................................... 362
7.1.2.1 L2 Filtering.............................................................................................................. 364
7.1.2.2 VLAN Filtering.......................................................................................................... 365
7.1.2.3 E-tag Filtering.......................................................................................................... 366
333369-007 17
Intel
®
Ethernet Controller X550 Datasheet
Contents
7.1.2.4 Manageability/Host Filtering....................................................................................... 366
7.1.3 Rx Queues Assignment .................................................................................................... 367
7.1.3.1 Queuing in a Non-virtualized Environment ................................................................... 368
7.1.3.2 Queuing in a Virtualized Environment.......................................................................... 369
7.1.3.3 L2 EtherType Filters.................................................................................................. 372
7.1.3.4 FCoE Redirection Table.............................................................................................. 374
7.1.3.5 SYN Packet Filters .................................................................................................... 375
7.1.3.6 Flow Director Filters.................................................................................................. 375
7.1.3.7 RSS........................................................................................................................ 387
7.1.4 Receive Data Storage in System Memory ........................................................................... 393
7.1.5 Receive Descriptors ......................................................................................................... 393
7.1.5.1 Legacy Receive Descriptor Format .............................................................................. 393
7.1.5.2 Advanced Receive Descriptors.................................................................................... 396
7.1.5.3 Receive Descriptor Fetching....................................................................................... 405
7.1.5.4 Receive Descriptor Write-Back ................................................................................... 406
7.1.5.5 Receive Descriptor Queue Structure............................................................................ 406
7.1.6 Receive Offloads ............................................................................................................. 409
7.1.6.1 Header Splitting ....................................................................................................... 409
7.1.6.2 Receive Packet Timestamp in Buffer............................................................................ 411
7.1.6.3 Receive Checksum Offloading .................................................................................... 412
7.1.6.4 SCTP Receive Offload................................................................................................ 413
7.1.6.5 Receive UDP Fragmentation Checksum........................................................................ 413
7.1.7 Receive Statistics ............................................................................................................ 414
7.1.7.1 General Rules .......................................................................................................... 414
7.1.7.2 Receive Statistics Hierarchy ....................................................................................... 415
7.2 Transmit Functionality ........................................................................................................... 416
7.2.1 Packet Transmission ........................................................................................................ 416
7.2.1.1 Transmit Storage in System Memory........................................................................... 416
7.2.1.2 Transmit Path in the X550 ......................................................................................... 417
7.2.2 Transmit Contexts........................................................................................................... 425
7.2.3 Transmit Descriptors ....................................................................................................... 425
7.2.3.1 Introduction ............................................................................................................ 425
7.2.3.2 Transmit Descriptors Formats .................................................................................... 425
7.2.3.3 Transmit Descriptor Ring........................................................................................... 437
7.2.3.4 Transmit Descriptor Fetching ..................................................................................... 438
7.2.3.5 Transmit Write Back ................................................................................................. 439
7.2.4 TCP and UDP Segmentation.............................................................................................. 441
7.2.4.1 Assumptions and Restrictions..................................................................................... 441
7.2.4.2 Transmission Process................................................................................................ 441
7.2.4.3 TCP and UDP Segmentation Performance..................................................................... 442
7.2.4.4 Packet Format ......................................................................................................... 443
7.2.4.5 TCP and UDP Segmentation Indication ........................................................................ 443
7.2.4.6 Transmit Checksum Offloading with TCP and UDP Segmentation..................................... 445
7.2.4.7 IP/TCP/UDP Header Updating..................................................................................... 445
7.2.5 Transmit Checksum Offloading in Non-Segmentation Mode ................................................... 448
7.2.5.1 IP Checksum ........................................................................................................... 448
7.2.5.2 TCP and UDP Checksum ............................................................................................ 449
7.2.5.3 SCTP CRC Offloading ................................................................................................ 449
7.2.5.4 Checksum Supported per Packet Types ....................................................................... 450
7.2.6 Transmit Statistics .......................................................................................................... 451
7.2.6.1 General Notes.......................................................................................................... 451
7.2.6.2 Transmit Statistics Hierarchy ..................................................................................... 451
7.3 Interrupts ............................................................................................................................ 453
7.3.1 Interrupt Registers.......................................................................................................... 453
7.3.1.1 Physical Function (PF) Registers ................................................................................. 453
Intel
®
Ethernet Controller X550 Datasheet
Contents
18 333369-007
7.3.1.2 Virtual Function (VF) Registers ................................................................................... 454
7.3.1.3 Extended Interrupt Cause (EICR) Registers.................................................................. 454
7.3.1.4 Extended Interrupt Cause Set (EICS) Register.............................................................. 454
7.3.1.5 Extended Interrupt Mask Set and Read (EIMS) Register, and Extended Interrupt Mask Clear
(EIMC) Register ....................................................................................................... 455
7.3.1.6 Extended Interrupt Auto Clear Enable (EIAC) Register................................................... 455
7.3.1.7 Extended Interrupt Auto Mask Enable (EIAM) Register................................................... 456
7.3.2 Interrupt Moderation ....................................................................................................... 456
7.3.2.1 Time-Based Interrupt Throttling — ITR........................................................................ 456
7.3.2.2 Immediate Interrupt................................................................................................. 458
7.3.3 TCP Timer Interrupt......................................................................................................... 458
7.3.3.1 Introduction ............................................................................................................ 458
7.3.3.2 Description.............................................................................................................. 458
7.3.4 Mapping of Interrupt Causes............................................................................................. 458
7.3.4.1 Legacy and MSI Interrupt Modes ................................................................................ 458
7.3.4.2 MSI-X Mode in Non-IOV Mode .................................................................................... 459
7.3.4.3 MSI-X Interrupts in IOV Mode .................................................................................... 461
7.4 802.1q VLAN Support ............................................................................................................ 465
7.4.1 802.1q VLAN Packet Format ............................................................................................. 465
7.4.2 802.1q Tagged Frames .................................................................................................... 465
7.4.3 Transmitting and Receiving 802.1q Packets ........................................................................ 466
7.4.3.1 Adding 802.1q Tags on Transmits............................................................................... 466
7.4.3.2 Stripping 802.1q Tags on Receives ............................................................................. 466
7.4.4 802.1q VLAN Packet Filtering ............................................................................................ 466
7.4.5 Double VLAN and Single VLAN Support .............................................................................. 467
7.4.5.1 Cross Functionality with Manageability ........................................................................ 467
7.4.5.2 Transmit Functionality............................................................................................... 467
7.4.5.3 Receive Handling of Packets with VLAN Header(s)......................................................... 468
7.4.5.4 Packets with No VLAN Headers in Double VLAN Mode .................................................... 469
7.4.5.5 Packets with Two VLAN Headers Not in Double VLAN Mode ............................................ 469
7.4.6 E-tag and VLAN .............................................................................................................. 469
7.4.6.1 Transmit Functionality............................................................................................... 469
7.4.6.2 Receive Handling of Packets with External Tags............................................................ 470
7.4.6.3 Cross Functionality with Manageability ........................................................................ 470
7.4.6.4 Packet User Priority (802.1P) Bits Handling.................................................................. 470
7.5 TLP Processing Hints (TPH) ..................................................................................................... 471
7.5.1 Steering Tag and Processing Hint Programming................................................................... 471
7.6 Data Center Bridging (DCB) .................................................................................................... 472
7.6.1 Overview ....................................................................................................................... 472
7.6.2 Transmit-Side Capabilities ................................................................................................ 474
7.6.2.1 Transmit Rate Scheduler (RS) .................................................................................... 474
7.6.2.2 User Priority to Traffic Class Mapping .......................................................................... 477
7.6.2.3 VM-Weighted Round-Robin Arbiters ............................................................................ 477
7.6.2.4 Tx TC Weighted Strict Priority Arbiters ........................................................................ 479
7.6.3 Receive-Side Capabilities.................................................................................................. 486
7.6.3.1 User Priority to Traffic Class Mapping .......................................................................... 486
7.6.3.2 Rx PB Weighted Strict Priority Arbiter.......................................................................... 487
7.7 Time SYNC (IEEE1588 and 802.1AS) ....................................................................................... 490
7.7.1 Overview ....................................................................................................................... 490
7.7.2 Flow and Hardware/Software Responsibilities ...................................................................... 490
7.7.2.1 Time Sync Indications in Rx and Tx Packet Descriptors.................................................. 492
7.7.3 Hardware Time Sync Elements.......................................................................................... 492
7.7.3.1 System Time Structure and Mode of Operation............................................................. 492
7.7.3.2 Time Stamping Mechanism ........................................................................................ 493
7.7.4 Hardware Time Sync Elements.......................................................................................... 494
333369-007 19
Intel
®
Ethernet Controller X550 Datasheet
Contents
7.7.4.1 Target Time............................................................................................................. 495
7.7.4.2 Time Stamp Events .................................................................................................. 496
7.7.5 Time Sync Interrupts....................................................................................................... 497
7.7.6 PTP Packet Structure ....................................................................................................... 497
7.7.6.1 Time Sync Packets Identification Configuration............................................................. 500
7.7.7 Virtualization .................................................................................................................. 501
7.7.8 Overview ....................................................................................................................... 501
7.7.8.1 Direct Assignment Model ........................................................................................... 501
7.7.8.2 System Overview ..................................................................................................... 502
7.7.9 PCI-SIG SR-IOV Support.................................................................................................. 505
7.7.9.1 SR-IOV Concepts ..................................................................................................... 505
7.7.9.2 Configuration Space Replication ................................................................................. 505
7.7.9.3 FLR Capability.......................................................................................................... 507
7.7.9.4 Error Reporting ........................................................................................................ 507
7.7.9.5 Alternative Routing ID (ARI) and IOV Capability Structures............................................ 509
7.7.9.6 RID Allocation.......................................................................................................... 509
7.7.9.7 Hardware Resources Assignment ................................................................................ 510
7.7.9.8 CSR Organization ..................................................................................................... 511
7.7.9.9 SR IOV Control ........................................................................................................ 512
7.7.9.10 DMA ....................................................................................................................... 514
7.7.9.11 Timers .................................................................................................................... 514
7.7.9.12 Power Management and Wake-Up .............................................................................. 514
7.7.9.13 Link Control............................................................................................................. 515
7.7.10 Packet Switching............................................................................................................. 515
7.7.10.1 Assumptions............................................................................................................ 515
7.7.10.2 Pool Selection .......................................................................................................... 516
7.7.10.3 Rx Packets Switching ................................................................................................ 516
7.7.10.4 Tx Packets Switching ................................................................................................ 519
7.7.10.5 Mirroring Support..................................................................................................... 522
7.7.10.6 Offloads .................................................................................................................. 522
7.7.10.7 Rate Control Features ............................................................................................... 523
7.7.10.8 Small Packets Padding .............................................................................................. 524
7.7.10.9 Switch Control ......................................................................................................... 524
7.7.11 Security Features ............................................................................................................ 525
7.7.11.1 Inbound Security...................................................................................................... 525
7.7.11.2 Outbound Security ................................................................................................... 525
7.7.11.3 Malicious Driver Detection ......................................................................................... 527
7.7.12 Virtualization of Hardware ................................................................................................ 530
7.7.12.1 Per-Pool Statistics .................................................................................................... 530
7.8 Tunneling Support ................................................................................................................. 530
7.9 Receive Side Coalescing (RSC) ................................................................................................ 531
7.9.1 Packet Candidacy for RSC ................................................................................................ 533
7.9.2 Flow Identification and RSC Context Matching ..................................................................... 535
7.9.3 Processing New RSC ........................................................................................................ 536
7.9.3.1 RSC Context Setting ................................................................................................. 536
7.9.4 Processing Active RSC ..................................................................................................... 536
7.9.5 Packet DMA and Descriptor Write Back............................................................................... 538
7.9.5.1 RSC Descriptor Indication (Write Back) ....................................................................... 539
7.9.5.2 Received Data DMA .................................................................................................. 539
7.9.5.3 RSC Header............................................................................................................. 539
7.9.5.4 Large Receive Data................................................................................................... 539
7.9.6 RSC Completion and Aging ............................................................................................... 540
7.10 Fibre Channel over Ethernet (FCoE) ......................................................................................... 542
7.10.1 Introduction ................................................................................................................... 542
7.10.1.1 FC Terminology........................................................................................................ 542
Intel
®
Ethernet Controller X550 Datasheet
Contents
20 333369-007
7.10.2 FCoE Transmit Operation.................................................................................................. 543
7.10.2.1 FCoE Transmit Cross Functionality .............................................................................. 543
7.10.2.2 FC Padding Insertion................................................................................................. 543
7.10.2.3 SOF Placement ........................................................................................................ 544
7.10.2.4 EOF Insertion .......................................................................................................... 544
7.10.2.5 FC CRC Insertion...................................................................................................... 545
7.10.2.6 Host Data Buffers Content for a Single Packet Send ...................................................... 545
7.10.2.7 FC TSO ................................................................................................................... 546
7.10.3 FCoE Receive Operation ................................................................................................... 548
7.10.3.1 FCoE Receive Cross Functionality................................................................................ 548
7.10.3.2 FC Receive CRC Offload............................................................................................. 549
7.10.3.3 Large FC Receive...................................................................................................... 550
7.11 Reliability ............................................................................................................................. 563
7.11.1 Memory Integrity Protection ............................................................................................. 563
7.11.2 PCIe Error Handling......................................................................................................... 563
7.12 IPsec Support ....................................................................................................................... 564
7.12.1 Overview ....................................................................................................................... 564
7.12.2 Hardware Features List .................................................................................................... 564
7.12.2.1 Main Features.......................................................................................................... 564
7.12.2.2 Cross Features......................................................................................................... 565
7.12.3 Software/Hardware Demarcation....................................................................................... 567
7.12.4 IPsec Formats Exchanged Between Hardware and Software .................................................. 568
7.12.4.1 Single Send............................................................................................................. 568
7.12.4.2 Single Send with TCP/UDP Checksum Offload............................................................... 568
7.12.4.3 TSO TCP/UDP .......................................................................................................... 569
7.12.5 Tx SA Table.................................................................................................................... 572
7.12.5.1 Tx SA Table Structure............................................................................................... 572
7.12.5.2 Access to Tx SA Table............................................................................................... 572
7.12.6 Tx Hardware Flow ........................................................................................................... 573
7.12.6.1 Single Send Without TCP/UDP Checksum Offload.......................................................... 573
7.12.6.2 Single Send With TCP/UDP Checksum Offload .............................................................. 573
7.12.6.3 TSO TCP/UDP .......................................................................................................... 574
7.12.7 AES-128 Operation in Tx.................................................................................................. 575
7.12.7.1 AES-128-GCM for ESP — Both Authenticate and Encryption............................................ 576
7.12.7.2 AES-128-GMAC for ESP — Authenticate Only ............................................................... 576
7.12.7.3 AES-128-GMAC for AH — Authenticate Only................................................................. 576
7.12.8 Rx Descriptors ................................................................................................................ 576
7.12.9 Rx SA Tables .................................................................................................................. 576
7.12.9.1 Rx SA Tables Structure ............................................................................................. 576
7.12.9.2 Access to Rx SA Tables ............................................................................................. 578
7.12.10 Rx Hardware Flow without TCP/UDP Checksum Offload......................................................... 578
7.12.11 Rx Hardware Flow with TCP/UDP Checksum Offload ............................................................. 579
7.12.12 AES-128 Operation in Rx.................................................................................................. 580
7.12.12.1 Handling IPsec Packets in Rx ..................................................................................... 580
Chapter 8 Programming Interface ............................................................................... 581
8.1 General ............................................................................................................................... 581
8.1.1 Memory-Mapped Access................................................................................................... 581
8.1.1.1 Memory-Mapped Access to Internal Registers and Memories .......................................... 581
8.1.1.2 Memory-Mapped Accesses to Flash ............................................................................. 581
8.1.1.3 Memory-Mapped Access to MSI-X Tables ..................................................................... 581
8.1.1.4 Memory-Mapped Access to Expansion ROM.................................................................. 582
8.1.2 I/O-Mapped Access ......................................................................................................... 582
8.1.2.1 IOADDR (I/O Offset 0x00; RW) .................................................................................. 582
8.1.2.2 IODATA (I/O Offset 0x04; RW) .................................................................................. 582
8.1.2.3 Undefined I/O Offsets ............................................................................................... 583
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