333369-007 19
Intel
®
Ethernet Controller X550 Datasheet
Contents
7.7.4.1 Target Time............................................................................................................. 495
7.7.4.2 Time Stamp Events .................................................................................................. 496
7.7.5 Time Sync Interrupts....................................................................................................... 497
7.7.6 PTP Packet Structure ....................................................................................................... 497
7.7.6.1 Time Sync Packets Identification Configuration............................................................. 500
7.7.7 Virtualization .................................................................................................................. 501
7.7.8 Overview ....................................................................................................................... 501
7.7.8.1 Direct Assignment Model ........................................................................................... 501
7.7.8.2 System Overview ..................................................................................................... 502
7.7.9 PCI-SIG SR-IOV Support.................................................................................................. 505
7.7.9.1 SR-IOV Concepts ..................................................................................................... 505
7.7.9.2 Configuration Space Replication ................................................................................. 505
7.7.9.3 FLR Capability.......................................................................................................... 507
7.7.9.4 Error Reporting ........................................................................................................ 507
7.7.9.5 Alternative Routing ID (ARI) and IOV Capability Structures............................................ 509
7.7.9.6 RID Allocation.......................................................................................................... 509
7.7.9.7 Hardware Resources Assignment ................................................................................ 510
7.7.9.8 CSR Organization ..................................................................................................... 511
7.7.9.9 SR IOV Control ........................................................................................................ 512
7.7.9.10 DMA ....................................................................................................................... 514
7.7.9.11 Timers .................................................................................................................... 514
7.7.9.12 Power Management and Wake-Up .............................................................................. 514
7.7.9.13 Link Control............................................................................................................. 515
7.7.10 Packet Switching............................................................................................................. 515
7.7.10.1 Assumptions............................................................................................................ 515
7.7.10.2 Pool Selection .......................................................................................................... 516
7.7.10.3 Rx Packets Switching ................................................................................................ 516
7.7.10.4 Tx Packets Switching ................................................................................................ 519
7.7.10.5 Mirroring Support..................................................................................................... 522
7.7.10.6 Offloads .................................................................................................................. 522
7.7.10.7 Rate Control Features ............................................................................................... 523
7.7.10.8 Small Packets Padding .............................................................................................. 524
7.7.10.9 Switch Control ......................................................................................................... 524
7.7.11 Security Features ............................................................................................................ 525
7.7.11.1 Inbound Security...................................................................................................... 525
7.7.11.2 Outbound Security ................................................................................................... 525
7.7.11.3 Malicious Driver Detection ......................................................................................... 527
7.7.12 Virtualization of Hardware ................................................................................................ 530
7.7.12.1 Per-Pool Statistics .................................................................................................... 530
7.8 Tunneling Support ................................................................................................................. 530
7.9 Receive Side Coalescing (RSC) ................................................................................................ 531
7.9.1 Packet Candidacy for RSC ................................................................................................ 533
7.9.2 Flow Identification and RSC Context Matching ..................................................................... 535
7.9.3 Processing New RSC ........................................................................................................ 536
7.9.3.1 RSC Context Setting ................................................................................................. 536
7.9.4 Processing Active RSC ..................................................................................................... 536
7.9.5 Packet DMA and Descriptor Write Back............................................................................... 538
7.9.5.1 RSC Descriptor Indication (Write Back) ....................................................................... 539
7.9.5.2 Received Data DMA .................................................................................................. 539
7.9.5.3 RSC Header............................................................................................................. 539
7.9.5.4 Large Receive Data................................................................................................... 539
7.9.6 RSC Completion and Aging ............................................................................................... 540
7.10 Fibre Channel over Ethernet (FCoE) ......................................................................................... 542
7.10.1 Introduction ................................................................................................................... 542
7.10.1.1 FC Terminology........................................................................................................ 542