Warford第五版：计算机系统详解 - 软硬件核心概念

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《计算机系统：核心概念及软硬件实现》第五版是由J. Stanley Warford撰写，专为理解计算机系统的精髓和其在实际应用中的软硬件交互设计的权威教材。该书作为英文原著，深入探讨了计算机体系结构的基础知识，涵盖了操作系统、处理器、内存管理、输入/输出设备、网络通信以及软件工程的核心内容。本书强调了计算机系统的五个关键组成部分：硬件、操作系统、编译器、程序设计语言和数据结构。作者以通俗易懂的方式解释了硬件组件如何协同工作，例如CPU如何执行指令、内存如何存储数据、以及I/O设备如何与系统进行交互。此外，书中还详细讨论了处理器架构，如冯·诺依曼体系结构，以及现代计算机如何处理并行计算和分布式系统。在软件层面，读者可以学习到操作系统的作用，如Windows、Linux或Unix等，它们如何管理硬件资源，提供用户界面，以及支持多任务和虚拟化。同时，书中会涉及编译器的工作原理，解释源代码如何转换为可执行代码的过程。此外，编程语言和数据结构是软件开发的基础，作者会介绍诸如C、C++、Java等语言的核心特性，并阐述算法和数据结构对程序性能的影响。对于网络通信，本书会讲解TCP/IP协议栈，包括网络层、传输层、应用层，以及互联网是如何连接全球设备的。此外，随着云计算和大数据的兴起，书中还会涉及分布式系统和云计算平台的基本概念，让读者了解现代计算机系统如何支撑这些新兴技术。版权方面，本书受2017年Jones&Bartlett Learning公司所有，任何未经许可的复制或利用都必须遵循严格的版权规定。对于批量购买或特殊折扣信息，企业或组织可通过提供的联系方式联系专门销售部门获取详情。《计算机系统：核心概念及软硬件实现》第五版是一本全面而深入的计算机科学入门书籍，无论对于初学者还是专业技术人员，都是理解和掌握计算机系统运作原理的重要参考资料。

The von Neumann Cycle
The Store Byte Direct Instruction
Bus Protocols
The Store Word Direct Instruction
The Add Immediate Instruction
The Load Word Indirect Instruction
The Arithmetic Shift Right Instruction
The CPU Control Section
12.2     Performance
The Data Bus Width and Memory Alignment
Memory Alignment
The Definition of an n-Bit Computer
Cache Memories
The System Performance Equation
RISC Versus CISC
12.3     The MIPS Machine
The Register Set
The Addressing Modes
The Instruction Set
MIPS Computer Organization
Pipelining
12.4     Conclusion
Simplifications in the Model
The Big Picture
Chapter Summary
Exercises
Problems
Appendix
Solutions to Selected Exercises
Index

depends on the mechanism of memory allocation on the run-time stack. A fairly detailed explanation

is given on the details of the memory allocation process for function calls, as this mechanism is

revisited at a lower level of abstraction later in the book.

Level ISA3

Level ISA3 is the instruction set architecture level. Its two chapters describe Pep/9, a virtual

computer designed to illustrate computer concepts. Pep/9 is a small complex instruction set computer

(CISC); a von Neumann machine. The central processing unit (CPU) contains an accumulator, an

index register, a program counter, a stack pointer, and an instruction register. It has eight addressing

modes: immediate, direct, indirect, stack-relative, stack-relative deferred, indexed, stack-indexed,

and stack-deferred indexed. The Pep/9 operating system, in simulated read-only memory (ROM), can

load and execute programs in hexadecimal format from students’ text files. Students run short

programs on the Pep/9 simulator and learn that executing a store instruction to ROM does not change

the memory value.

Students learn the fundamentals of information representation and computer organization at the bit

level. Because a central theme of this book is the relationship of the levels to one another, the Pep/9

chapters show the relationship between the ASCII representation (Level ISA3) and C variables of

type char (Level HOL6). They also show the relationship between two’s complement representation

(Level ISA3) and C variables of type int (Level HOL6).

Level Asmb5

Level Asmb5 is the assembly level. The text presents the concept of the assembler as a translator

between two levels—assembly and machine. It introduces Level Asmb5 symbols and the symbol

table.

The unified approach really comes into play here. Chapters 5 and 6 present the compiler as a

translator from a high-order language to assembly language. Previously, students learned a specific

Level HOL6 language, C, and a specific von Neumann machine, Pep/9. These chapters continue the

theme of relationships between the levels by showing the correspondence between (a) assignment

statements at Level HOL6 and load/store instructions at Level Asmb5, (b) loops and if statements at

Level HOL6 and branching instructions at Level Asmb5, (c) arrays at Level HOL6 and indexed

addressing at Level Asmb5, (d) procedure calls at Level HOL6 and the run-time stack at Level

Asmb5, (e) function and procedure parameters at Level HOL6 and stack-relative addressing at Level

Asmb5, (f) switch statements at Level HOL6 and jump tables at Level Asmb5, and (g) pointers at Level

HOL6 and addresses at Level Asmb5.

The beauty of the unified approach is that the text can implement the examples from the C chapter

at this lower level. For example, the run-time stack illustrated in the recursive examples of Chapter 2

corresponds directly to the hardware stack in Pep/9 main memory. Students gain an understanding of

the compilation process by translating manually between the two levels.

This approach provides a natural setting for the discussion of central issues in computer science.

For example, the book presents structured programming at Level HOL6 versus the possibility of

unstructured programming at Level Asmb5. It discusses the goto controversy and the structured

programming/efficiency tradeoff, giving concrete examples from languages at the two levels.

Chapter 7, “Language Translation Principles,” introduces students to computer science theory.

Now that students know intuitively how to translate from a high-level language to assembly language,

we pose the fundamental question underlying all of computing: What can be automated? The theory
naturally fits in here because students now know what a compiler (an automated translator) must do.
They learn about parsing and finite-state machines—deterministic and nondeterministic—in the
context of recognizing C and Pep/9 assembly language tokens. This chapter includes an automatic
translator between two small languages, which illustrates lexical analysis, parsing, and code
generation. The lexical analyzer is an implementation of a finite-state machine. What could be a more
natural setting for the theory?
Level OS4
Level OS4 consists of two chapters on operating systems. Chapter 8 is a description of process
management. Two sections, one on loaders and another on trap handlers, illustrate the concepts with
the Pep/9 operating system. Seven instructions have unimplemented opcodes that generate software
traps. The operating system stores the process control block of the user’s running process on the
system stack, and the interrupt service routine interprets the instruction. The classic state transition
diagram for running and waiting processes in an operating system is thus reinforced with a specific
implementation of a suspended process. The chapter concludes with a description of concurrent
processes and deadlocks. Chapter 9 describes storage management, both main memory and disk
memory.
Level LG1
Level LG1 uses two chapters to present combinational and sequential circuits. Chapter 10 emphasizes
the importance of the mathematical foundation of computer science by starting with the axioms of
Boolean algebra. It shows the relationship between Boolean algebra and logic gates and then
describes some common logic devices, including a complete logic design of the Pep/9 arithmetic
logic unit (ALU). Chapter 11 illustrates the fundamental concept of a finite-state machine through the
state transition diagrams of sequential circuits. It concludes with a description of common computer
subsystems such as bidirectional buses, memory chips, and two-port memory banks.
Level Mc2
Chapter 12 describes the microprogrammed control section of the Pep/9 CPU. It gives the control
sequences for a few sample instructions and addressing modes and provides a large set of exercises
for the others. It also presents concepts of load/store architectures, contrasting the MIPS reduced
instruction set computer (RISC) machine with the Pep/9 CISC machine. It concludes with
performance issues by describing cache memories, pipelining, dynamic branch prediction, and
superscalar machines.
Use in a Course
This book offers such broad coverage that instructors may wish to omit some of the material when
designing a course. I use Chapters 1–7 in a computer systems course and Chapters 10–12 in a
computer organization course.
In the book, Chapters 1–5 must be covered sequentially. Chapters 6 (“Compiling to the Assembly
Level”) and 7 (“Language Translation Principles”) can be covered in either order. I often skip ahead
to Chapter 7 to initiate a large software project, writing an assembler for a subset of Pep/9 assembly

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